Video safety helmet based on DSP collaborative video stream processing technology

In order to improve the controllability of on-site operations in high-risk workplaces, this paper adopts the principle of bionics and highly integrated design to realize a 3G video helmet with the same view angle as the human eye. This design is composed of two parts: a video safety helmet and a waist-span data processing terminal, which are connected by a high-reliability aviation plug. The image processing is composed of Samsung’s S3C6410 ARM11 processor and TMS320DM642 DSP processor.

1 Introduction

In order to improve the controllability of on-site operations in high-risk workplaces, this paper adopts the principle of bionics and highly integrated design to realize a 3G video helmet with the same view angle as the human eye. This design is composed of two parts: a video safety helmet and a waist-span data processing terminal, which are connected by a high-reliability aviation plug. The image processing is composed of Samsung’s S3C6410 ARM11 processor and TMS320DM642 DSP processor. This design combines the advantages of the DSP processor in video compression and the outstanding performance of the Linux operating system running on ARM in the data management and task scheduling mechanism. The DSP completes the image processing function and transmits the video data to the Embedded micro-processing system completes the transmission and storage functions of video data.

2. System composition

The design consists of two parts: a video safety helmet and a waist-span video terminal. The video helmet contains 1 video input, 1 audio input and 1 audio output, and is equipped with auxiliary lights. The waist-span video terminal is mainly composed of ARM11 and DSP dual-core system, 3G wireless module and power management module, which mainly completes data processing, transmission, storage and system control functions.

2.1 ARM processing system design

The ARM processing system is mainly composed of a main control module, a data storage system, and an analog and digital signal acquisition module.

The CPU adopts Samsung S3C6410A processor, the highest operating frequency can reach 667MHz.

2.2 DSP video processing system design

The DSP image processing system consists of three parts, video decoding and image processing. Video decoding uses TVP5150 ultra-low power decoder, image processing uses TMS320DM642 (DM642 for short) DSP processor, which can work at a clock frequency of 600MHz, the instruction cycle is 1.67ns, and each instruction cycle can parallel 8 32-bit instructions , The processing capacity can reach the peak calculation speed of 4800MIPS.

After the camera analog signal is decoded by TVP5150, it is sent to the DM642 chip for H.264 video compression. The compressed signal is sent to the ARM embedded system and the data is sent to the remote server or local storage through the 3G module.

2.3 Cooperative realization between ARM system and DSP system

As shown in Figure 1, the video signal is compressed and encoded by the DSP through the host interface (HPI) to transmit the data to the S3C6410A for the next step of data transmission or storage. The circuit diagram is shown in Figure 2.

Video safety helmet based on DSP collaborative video stream processing technology

This article selects HPI16 mode, the main interface signal lines are as follows:

(1) 16-bit data line HD[15:0], These data lines are in a high-impedance state when the HPI read and write function is not used.

(2) 2 access control selection signal lines HCNTL[1:0].

Its state is used to control which of the three HPI registers is currently accessed, HCNTL[1:0]=00, the host reads and writes the HPIC register: HCNTL[1:0]=01, the host performs a unique Display operation on the HPLA register; HCNTL[1:0]=10, the host reads and writes the HPID register in a way that resists automatic increase. Every time HPID is read yi times, HPIA automatically adds a word to resist (4 bytes); HCNTL[1:0]=11, the host reads and writes the HPID register in a fixed address mode, and the HPIA register address remains unchanged.

(3) Half-word recognition selection signal line HHWIL. Since the smallest storage unit of DM642 is a word (32bit), when HPI is configured as HPI16, it is necessary to continuously transmit two half-words to form a word and send it to the host. The HHWIL signal line is used to distinguish the first Whether to pass the high halfword or the low halfword.

(4) Address strobe input signal line HAS. This signal is used for the multiplexing of the data line and address line of the host. This signal should be connected high when not in use.

(5) The host read and write select signal line HR/W. The host must set HR/W to high for read operations and low for write HPI operations.

(6) Three strobe signal lines HCS, HDS1 and HDS2. These three signal lines are combined on-chip into a low-level effective strobe signal HSTROBE.

(7) Prepare the signal line HRDY. When the signal line is low, it indicates that HPI is ready to transmit data.

(8) Send the interrupt signal line HINT to the host.

As shown in Figure 2, the S3C6410 Bank1 chip select signal nCS7 is connected to nHCS, and the HPI interface is mapped to the corresponding kernel space of S3C6410 as an external physical address. The Bank1 address space is from 0×08000000 to 0x0fffffff and the read and write signals nOE and nWE are respectively Receive nHDS1 and nHDS2. What this system adopts is HPll6 mode, the 32-bit data is divided into low 16 bits and high 16 bits to store separately, here adopts ADDR5 to control the nibble identification selection. Connecting AB2 and AB3 of S3C6410 to HCNTL0 and HCNTL1 can easily address the three registers of HPI, HPIC, HPIA, and HPID. ADDR6 is connected to HR/W of DM642, and HPI read and write strobe is realized by controlling this address line. HRDY is inverted and connected to WAIT signal line. HINT of DM642 is directly connected to the external interrupt IRQ5 pin of S3C6410 to achieve DSP interrupts the transmission of signals to the host.

After testing, based on HPI16 data transmission protocol, the communication rate between DM642 and S3C6410 can reach 50Mbps, and the bandwidth is enough to transmit MPEG and other compressed video data.

3. Summary

The 3G video safety helmet based on the ARM11 and DSP collaborative video stream processing technology designed in this paper is used in field operations in the petroleum and electric power industries. The article adopts the transmission mode of HPll6, its transmission speed can better meet the actual demand, the follow-up will try to adopt the HP132 mode, the transmission speed will be further improved. In the communication between ARM and DSP, through the introduction of video data communication protocol, compared with the traditional communication through read/write buffer, the reliability of video data transmission is better guaranteed.

The Links:   SKIIP26AC126V1 FZ800R12KF4

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