Using clock multiplexing technology to improve the fault coverage of testability design

The design for test technology based on the scan path method is an important method of the design for test (DFT) technology. This method can set the state of each flip-flop in the circuit from the outside of the chip, and through the design of a simple scan chain , Scan to observe whether the trigger is working in a normal state, in order to detect the correctness of the circuit. However, with the development of digital circuits in the direction of ultra-large scale, the number of flip-flops used in the design of circuits is also increasing. How to adopt appropriate testability design strategies to detect more flip-flops has become based on the scan path method. A key question.

The design for test technology based on the scan path method is an important method of the design for test (DFT) technology. This method can set the state of each flip-flop in the circuit from the outside of the chip, and through the design of a simple scan chain , Scan to observe whether the trigger is working in a normal state, in order to detect the correctness of the circuit. However, with the development of digital circuits in the direction of ultra-large scale, the number of flip-flops used in the design of circuits is also increasing. How to adopt appropriate testability design strategies to detect more flip-flops has become based on the scan path method. A key question.

This article uses the testability design technology based on the scan path method to design the testability of an actual circuit of about 7.5 million gate-level radar chips. In the design, by using several effective design strategies such as clock multiplexing technology, clock circuit processing technology and IP isolation technology, the fault coverage of the chip is greatly improved, and the goal of design for testability is finally achieved.

1 Scan chain design principle

The digital circuit is composed of a large number of combination components and sequential components, and the sequential components are embodied as a single flip-flop (DFF). The basic composition of the digital circuit is shown in Figure 1. The system clock (CP) controls the input and output of the corresponding data of the data port of each flip-flop.

The testability design based on the scan path method is to replace the sequential element flip-flop in the circuit with the corresponding scanable sequential element scan flip-flop (SDFF); then connect the output terminal (Q) of the upper scan flip-flop to the lower The data input terminal (SDI) forms a test serial shift register from input to output, that is, the scan chain (ScanChain); through the control of the CP terminal clock, the test of sequential components and combinational logic is realized. The circuit after the realization of the scan chain design is shown in Figure 2.

Using clock multiplexing technology to improve the fault coverage of testability design 

After adopting the scanning design technology, under the control of the scanning control terminal (SEN) and the clock terminal, through the scanning data input terminal, the required data can be serially shifted to the scanning register unit, and each unit can be controlled serially; at the same time, They can be observed serially through the scan output (Scan_out). This increases the controllability and observability of the sequential circuit.

2 Scan chain strategy design

The dotted line in Figure 2 is the scan flip-flop, that is, the basic component of the scan chain. The principle of its composition is shown in Figure 3.

Using clock multiplexing technology to improve the fault coverage of testability design

Before the scan chain is designed, the flip-flops in the circuit are controlled by the system clock port to control the data changes, so when the scan design is done, more flip-flops can be detected through the system clock multiplexing to achieve the purpose of controlling the scan flip-flops. .

For the same reason, the flip-flops in some special circuits are also connected in series with the scan chain manually or by software, so as to increase the number of flip-flops that can be scanned, and ultimately improve the fault coverage. But it should be noted that the prerequisite for the application of these design-for-test strategies is that the original design cannot be changed.

3 Strategies used in the design

When designing the DFT and inserting the scan chain, an important issue is test coverage, and its final value is determined by the ratio of the total number of flip-flops to the number of flip-flops that can be tested, so whether it can Testing as many flip-flops in the radar chip circuit as possible has become a key issue in the design of the scan path method. According to the actual design circuit, the following three effective design strategies are proposed. According to the final test results, the test coverage can be greatly improved after adopting this design strategy to meet the design index needs.

3.1 Clock multiplexing technology

Each flip-flop is controlled by the system clock. The system clock can cover most of the flip-flop components in this design. Therefore, consider the use of clock multiplexing technology. When the scan chain is inserted for testing, the test clock is introduced to the system clock. The test clock can cover as many flip-flops as possible, and after inserting the scan chain, it is replaced with scan flip-flops. Its realization principle is shown as in Fig. 4.

It can be seen from the figure that the clock circuit generates many clocks with different frequencies to meet the needs of different modules. The corresponding selector (MUX) is added to the output port of the clock circuit to control the selection of the clock; when it is in the normal working state, the MUX selects The normal clock enters the corresponding module to realize the corresponding function; when in the scan state, these MUXs select the same scan test clock signal (Te cp) to enter each module for testing. The advantage of this is that it not only meets the needs of test selection, but also tests all triggers as much as possible to meet the needs of test coverage.

3.2 Special clock circuit processing

There are many special circuits in this design. Among them, there is a clock generating circuit that cannot be designed for testability of the scan path method. The specific circuit diagram is shown in Figure 5.

In this structure, the clock is output from the Q terminal of the second flip-flop and input to the clock (CP) terminal of the third flip-flop. Since the scan clock cannot control the third and subsequent flip-flops, the designed scan chain will not cover the subsequent circuits. As a result, the fault coverage rate will decrease, and the test coverage rate will also decrease.

The way to improve this circuit structure is to add a MUX selector manually or by software. When inserted in the scan chain, the normal control clock signal will enter the clock end of the third flip-flop. The circuit structure of concrete realization is shown as in Fig. 6.

Using this strategy, after inserting the scan chain, when the MUX selector is in the scan state, the scan clock will be connected to the subsequent flip-flops and connected to the scan chain, which will greatly improve the fault coverage rate, thereby Improve test coverage.

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3.3 IP isolation technology

Many IP modules are used in the design, and the synthesized netlist appears as a “black box” without specific circuits. The existence of these “black boxes” makes it impossible or difficult for some sequential combination circuits to be based on the scan path method. DFT design requires the use of other DFT design tools for testability design, such as the RAM and ROM memory modules used in this design.

Therefore, in order to ensure that the lower-level sequential circuit connected to the IP can be covered by the normally designed scan chain and increase the measurable range of the flip-flop, the solution adopted is to isolate such IP modules with software commands. The module carries on DFT design, its realization principle is shown as in Fig. 7.

Through this method, one or more similar IP modules can be softly isolated from the original circuit. When the circuit is working in the non-scanning state, data flows in and out of the IP module in the normal data flow direction; when the circuit is working in the scanning state, the scanned data bypasses the corresponding 1P module and flows into the lower-level sequential circuit according to the corresponding scan chain path Part, realize the function of scanning test.

This method does not destroy the structure of the original chip circuit and the functions realized as a whole, but also ensures the smooth progress of the DFT design and improves the coverage rate of the testability design of the chip.

4 Result analysis

4.1 Test results

When no design strategy is adopted, the test coverage of this chip can only reach about 30% to 40%, which is far from reaching the required performance indicators.

It can be seen from Figure 8 that when the above design strategy is adopted, the test coverage, fault coverage and ATPG coverage reach 96.95.9/6, 94.52% and 99.99, respectively. %.

4.2 Analysis of test results

In the test result data column shown in Figure 8, the data column on the left shows the total generated test vectors and the number of valid test vectors. The right side shows the number of various faults that can be measured during the scan chain test. The calculation formula for the fault coverage F is:

Among them: undetectable faults include discarding faults, fixed faults, redundant faults, etc. This design considers many fault models, including many fixed fault types (for example: the chip port is locked to a fixed value and cannot be detected) calculated into the above calculation formula, so the actual undetectable faults are more than the statistics in the tool The number is less; through the above analysis, it can be seen that the actual fault coverage rate that can be achieved is better than the test result.

5 Conclusion

In this paper, the circuit of a radar digital processing chip with about 7.5 million gates is designed for testability based on the scan path method. In the design, the clock multiplexing technology is used to make reasonable use of the existing circuits in view of the extremely large number of actual circuit gates. Design resources greatly increase the number of testable flip-flops; apply special processing strategies to special circuits to increase the fault coverage of testability design. It can be seen from the test results that compared with not adopting the design strategy mentioned above, the final test coverage has been significantly improved, the goal of the design strategy application has been achieved, and the design index requirements have finally been met.

The Links:   SKD110-08 LTM190E1-L03

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