Use FPGA and embedded soft core processor to realize high-performance criminal arrest system

As high-tech tools have become an increasingly critical part of criminal capture weapons, it is not surprising that law enforcement agencies and security professionals continue to seek faster and more convenient data collection and interpretation methods. The applications in this area are becoming more and more complex, and they must adapt to evolving requirements and keep costs within the limited budget of the organization. In view of this, a programmable logic (PLD) solution with high performance, flexibility and high cost-effectiveness is undoubtedly an ideal solution.

Two college student teams used FPGA and embedded soft-core processors to develop two prototypes of criminal capture systems. One is a police car support system with a wireless automatic tracking camera, and the other is a fingerprint recognition system to prevent the security system from being breached.
Keep your eyes on suspicious objects-even at high speeds
When the tracking operation is initiated, the police officer has only a short time to activate the siren, report to the control center, and communicate with other patrols. Because these things happen almost simultaneously, the police officers also rely on the vehicle tracking system to lock the fleeing criminals within line of sight. However, when suspects are rushing through heavy traffic, traditional tracking systems that use fixed-position cameras can easily lose their tracks. Therefore, there will be a need for an in-vehicle system that can keep an eye on suspicious vehicles while allowing police officers to share and receive information with colleagues at the scene and headquarters.
Use FPGA and embedded soft core processor to realize high-performance criminal arrest system
Figure 1: Design concept
A prototype of an onboard police vehicle support system developed by students from Inha/Hongik University of Aeronautics and Astronautics in South Korea. The integrated solution includes the following components:
Wireless automatic tracking system: Continuously track suspicious vehicles and Display the image of the vehicle in the center of the Display. A camera that moves in all directions uses a stepping motor controlled by FPGA to move up and down, left and right, and can capture fast-moving vehicles through rapid response.
Automatic voice warning system: Use embedded processor to realize MPEG audio decoding, which is used to warn escape suspects.
HSDPA function: Provide real-time data and image sharing.
FPGA-based interface to the onboard diagnostic system (OBD-II): used to monitor the engine performance parameters of police vehicles.
The organic combination of FPGA and embedded processor makes the system easy to realize image, voice, image and data processing.
Realize voice, video and data in a single system
In terms of technology platform, the design team used Altera’s DE2 development and teaching board, which includes Cyclone II FPGA, Quartus II design software and Nios II embedded processor.
A single Cyclone II FPGA supports the operation of the entire system, and can complete functions such as image processing, compression, data transmission, MPEG audio decoding, motor control, and OBD communication. All necessary components are assembled together using the SOPC Builder system design tool, allowing the design team to design a module, which can be modified or directly reused for other applications.
Use FPGA and embedded soft core processor to realize high-performance criminal arrest system
Figure 2: Architecture of the automatic tracking system
Auto tracking camera
The image processing module of the camera transmits the omni-directional movement command to the system stepper motor controller on the FPGA. According to such commands, the stepper motor controller can generate operating signal pulses, and then send these signals to each motor.
The camera’s image capture module converts the analog image information into the ITU656 standard digital stream on the DE2 board, and uses this data stream: to control the automatic tracking of the camera’s left, right, up and down operations; support video sharing systems and JPEG compression wireless Transmission; provide on-board display.
When the police officer needs to activate the camera’s tracking mode, he only needs to point the camera at the target vehicle and press a button on the DE2 board. Then the image processing module also running on the FPGA extracts the average color from the target vehicle and estimates its position. Once the vehicle starts to move, the omni-directional moving camera starts to track it. The system sends control commands to the motor controller every 30th of a second, and speed is one of its key advantages. The captured images are stored in a USB storage device and transmitted to the police command center at the same time. Of course, the tracking mode is only applicable during the day.
Real-time JPEG compression usually requires a high-performance DSP chip or ASSP. In this case, the design team used the Nios II C-to-Hardware Accelerated Compiler (C2H) to execute the libjpeg forward discrete cosine transform (DCT) function to meet the performance goals without the need for an external processor or DSP chip. The C2H compiler can convert time-critical ANSI C functions into hardware accelerators in FPGAs to improve their performance.
Use FPGA and embedded soft core processor to realize high-performance criminal arrest system
Figure 3: The principle block diagram of the automatic tracking system
Automatic voice warning

When the vehicle’s automatic tracking camera starts to work in the tracking mode, it will trigger the automatic voice warning function to turn on and warn the escape suspect. The 100MHz embedded processor on the DE2 board is used to play a customized instruction set of MPEG audio data. Initially playback performance was a problem, but by adding 6? bit custom instructions for multiplication in the Nios II soft-core processor, the design team increased the performance by 2.5 times.
Customized OBD-II interface
The interface connected to OBD-II not only penetrates the communication between automotive Electronic devices, but also connects the diagnostic tool to the engine control unit (ECU) to realize vehicle maintenance and monitoring. The SOPC Builder UART component is connected to the OBD-II interface to collect information such as vehicle speed, fuel status, and vehicle fault status.
Therefore, the design team can use the performance advantages of Nios II custom instructions and the acceleration function of C to hardware to create a high-performance system to provide help on site. Thanks to the use of FPGAs, the team can flexibly improve performance as needed, without increasing clock frequency and reducing power consumption, and without using high-speed designs. When the team encounters performance issues that require changes to the hardware design, they only need to reprogram the FPGA to deal with these changes.

Convert fingerprints into certificates for authentication
Fingerprint recognition technology has high cost performance and security, and supports various applications used to protect sensitive data and prevent unauthorized access to the system. Traditional fingerprint identification systems are based on PC or DSP chips. However, processing images on a PC is slow, and the DSP chip lacks the flexibility to support all the required functions. FPGA effectively fills the gap between high-performance processing and system flexibility. A student team from Huazhong University of Science and Technology in China created a prototype fingerprint recognition system using a DE2 board containing Cyclone II FPGA and Nios II processors. The system took full advantage of the high performance and flexibility of FPGA technology.

Fast and flexible system enhancements
Using the system-level programmable chip (SOPC) method, the team successfully developed a network fingerprint identification system with authentication and centralized management functions. The PC as the host runs software that provides various management functions. The 50MHz Nios II/f core embedded in Cyclone II FPGA runs related algorithms to realize various functions including system initialization, fingerprint collection, image processing, master-slave communication and user interface. With the support of SOPC Builder, the team can not only integrate various components into a single system in an efficient manner, but also configure each component as needed.
Use FPGA and embedded soft core processor to realize high-performance criminal arrest system
Figure 4: Sequence of fingerprint processing
The following is the working principle of the fingerprint recognition system: When the fingerprint collector detects the presence of a finger, it will wake up from sleep mode to collect images and submit the highest quality images. The 12.5MHz SPI core on the DE2 board transmits the image data to the embedded processor, and the processor executes the corresponding image processing algorithm to complete the following processing of the fingerprint:
Pattern discovery: The system first calculates the direction of a single point based on the grayscale values ​​of the points around the target point, and then uses statistical methods to obtain a 5×5 block pattern, and marks the block without clear conditions about the background.
Image filtering: The system will enhance the continuity of the image along the ridge, and at the same time increase the contrast of the image perpendicular to the ridge, so as to segment adjacent ridges.
Binarization: The ridges of the image will be very clear after filtering, so a fixed threshold binarization function can use a fixed gray value as a standard to segment the image into black and white versions.
Ridge thinning: At this stage, the image will go through a parallel thinning process, this process will gradually adjust the ridge line until the ridge line is thinned to the width of a single pixel, so as to prepare the image for detailed positioning.
Positioning details: In this last step, the system scans the pattern to locate the center point of the fingerprint. Starting from the refined ridge image, the system will locate the fingertip points and segment these points to evaluate the uniqueness of the fingerprint.
Through customized instructions and customized peripherals, the team greatly improved the performance of image processing algorithms. Since 52 multiply-accumulate operations are required, the design team designed a custom instruction that can complete a single multiply-accumulate operation in three clock cycles, thereby reducing the time of 36.4s when there is no custom instruction to 4.77 when using a custom instruction s, which improves image filtering performance by 7 times; ridge refinement requires 16 comparisons of target pixels. The team designed two custom peripherals, which can complete 16 comparisons in 6 clock cycles, so there will be no customization The 13.5s when the peripheral is used is shortened to 2.67s when there is a custom peripheral, which improves the performance by 5 times.
When someone provides their fingerprints and other identifying information at the terminal, the system will first look for matching information in the database to determine whether to allow access. The false acceptance rate of the system (the possibility of misjudging inconsistent fingerprints as consistent) is less than 5%. Its false rejection rate (the probability of judging a consistent fingerprint as inconsistent) is less than 20%.
Use PLD to dig deeper into criminals
Just like police cars support applications, DSP devices or ASSPs can also be used in fingerprint identification systems. However, the design team found that the processing speed can be greatly improved by simply implementing Nios II custom instructions and custom peripherals. On the basis of high-quality FPGA, the design team also integrated multiple components, thereby reducing the complexity, cost and power consumption of the solution.
Most applications require a certain degree of flexibility to meet performance and cost requirements. These teams demonstrated how to use hardware to accelerate algorithms, allowing operation at a lower clock frequency, thus effectively reducing power consumption and simplifying the overall design. At the same time, they also use system generation tools to help them easily reuse and modify components for other applications.
author: David Auyeung
Senior Embedded Product Marketing Engineer
Altera Corporation

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