The basic structure of phase-locked loop and its application in SDH equipment

SDH network as a digital network, the data transmitted are all digital streams. This feature requires that the network must be synchronized, that is, the clock frequency and phase of all switching nodes in the network are controlled within a predetermined tolerance range in order to make All digital streams of each switching node in the network are exchanged correctly and effectively. Otherwise, information bit overflow and emptying will occur in the buffer of the digital switch, which will cause sliding damage of the digital stream and cause data errors.

Authors: Hao Nurturing, Tang Puying

SDH (Synchronous Digital Series) is an optical synchronous digital transmission technology. It uses a unique frame structure to encapsulate digital streams into STM (synchronous transmission mode) signals for transmission. According to different needs, the transmission rate has different levels (STM-N). , N=1/4/16/64, respectively 155 Mbit/s, 622 Mbit/s, 2.5 Gbit/s and 2.5 Gbit/s). Many services of different formats can be encapsulated into STM frame structure for transmission in SDH networks, such as PDH, IP, and ATM. At this stage, SDH technology is widely used in the field of data transmission.

SDH network as a digital network, the data transmitted are all digital streams. This feature requires that the network must be synchronized, that is, the clock frequency and phase of all switching nodes in the network are controlled within a predetermined tolerance range in order to make All digital streams of each switching node in the network are exchanged correctly and effectively. Otherwise, information bit overflow and emptying will occur in the buffer of the digital switch, which will cause sliding damage of the digital stream and cause data errors.

In the synchronization technology, the application of phase-locked loop is very extensive, especially in the field of digital communication, the phase-locked loop has played a great role. This article starts with analyzing the characteristics of the phase-locked loop, and introduces the application of the phase-locked loop in SDH synchronization network in detail.

1 The characteristics of phase-locked loop

1.1 The basic composition of phase-locked loop

The phase locked loop is a phase negative feedback control system, which usually consists of three basic components: PD (phase detector), LF (loop filter) and VCO (voltage controlled oscillator). PD is a phase comparator, which compares the phases of two input signals, generates an error phase, and converts it into an error voltage Vd(f); LF is a low-pass filter used to filter out the high frequency components in Vd

The entire phase-locked loop performs continuous feedback adjustment on the phase of the local oscillation signal according to the phase error between the input signal and the local oscillation signal, so as to achieve the purpose of making the phase of the local oscillation signal track the phase of the input signal.

1.2 Mathematical model of phase-locked loop

Take the sinusoidal signal as an example to analyze the working principle of the phase-locked loop. Suppose the input signal is:

The basic structure of phase-locked loop and its application in SDH equipment

It can be seen from equation (7) that the frequency of the output signal is the same as the frequency of the input signal at this time, indicating that the loop has been locked.

In summary, the phase-locked loop has good tracking characteristics. If the loop parameters are selected appropriately; the output frequency can easily track the input frequency, so that the loop can be locked.

2 SDH network synchronization method

SDH networks generally use hierarchical master-slave synchronization, and the clock levels are divided into the following 4 categories by ITU-T:

a) Reference master clock: G. 811 standard is PRC, Primary Ref-erence Source;
b) Transfer and ending from the clock: G. The 812 specification is SSU-A, Primary-Synchronization Supply Unit;
c) End office slave clock: C. The 812 specification is SSU-B, Second Lev-el-SSU;
d) SDH equipment clock: c. The 813 standard is SEC, SDH EquIPMent Clock.

The clock structure usually adopts a tree structure, and each level of clock is synchronized with its previous level clock; among them, PRC (primary reference clock) is at the top of the tree structure, which is the highest level of clock in the network, with extremely high accuracy and stability Spend. The synchronization network sends the PRC signal to the switching nodes at all levels in the network, and then locks the local clock to the received PRC through the phase-locked loop, so that the clocks of the switching nodes in the network are synchronized with the PRC. At the same time, in order to maintain the stability of the network, multiple backups are used for PRC to prevent PRC from causing problems and causing network failures.

The SDH network divides the entire network into several synchronization areas, each synchronization area has its LPR (Regional Reference Clock), which conforms to G. 811 standard; LPR can receive the PRC of the entire network to achieve synchronization. Although each LPR has a difference, the difference is very small, so the areas are close to synchronization, which is called pseudo-synchronization. In the area, it is all transfers and endings. There is BITS (Building Integrated Timing System) in the bureau, which is in line with G. The 812 standard clock can also receive external higher-level clocks to trace to the PRC of the entire network. At the same time, it can also use SDH STM-N signals to transmit clock signals; then to the next level, the SDH equipment network elements in the office directly The timing is obtained from BITS, so that all network elements in the network are finally synchronized.

3 Clock function structure of SDH equipment

Among them: T1 is the STM-N input interface; T2 is the PDH input interface; T3 is the external timing input interface. The equipment cho obtains the input of external timing signals from T1, T2 and T3. Each selector has the function of selecting the optimal clock signal for the input, and selects the optimal clock signal according to the prefabricated conditions; at the same time, the device has a built-in SETC (synchronized device timing generator), that is, SEC (SDH device clock), and you can Generate a clock signal, which is a digital phase-locked loop, which can synchronize the high-level clock output by the selector B, thereby outputting a stable clock T0, which satisfies G. 812 requires that a system clock signal is provided for each part of the SDH device to achieve network synchronization; at the same time, the device also has the function of providing timing signals to other SDH devices. This part of the function is implemented by selector C, which selects from T0 and The optimal clock is selected in the device A, processed by the phase-locked loop, and finally the output satisfies G. 813 required timing signal T4.

4 Application of phase-locked loop in SDH equipment

From the above analysis, it can be seen that there are two places in the equipment that use the phase-locked loop, one is the system synchronous clock phase-locked loop, and the other is the derived clock phase-locked loop.

The upper part of the phase-locked loop is SETG, which is a digital phase-locked loop. The digital LF is implemented by CPU software, and the PD is implemented by FPGA; PD performs the timing reference signal selected by selector B and the signal generated by VCO frequency division. Digital phase discrimination, through CPU filter processing and D/A conversion to generate a control voltage, thereby controlling the frequency of the VCO, thus forming a feedback loop. When the frequency of the timing reference and the jitter drift performance are within a certain range, the local The VCO can be synchronized to the timing reference. The lower part of the block diagram is the phase-locked loop that outputs the clock. It is an analog phase-locked loop and does not involve software control. Its principle is the same as that of a digital phase-locked loop. It also finally outputs a stable clock signal locked to the input, which is other SDH. The clock input of the device.

5 PLL characteristic analysis

The biggest feature of this application is that the phase-locked loop SETG is controlled by the CPU software. Compared with the analog ring, the digital ring has the characteristics of convenient parameter adjustment, fast locking, and stable performance. More importantly, this solution makes the working range of SDH equipment network elements wider and more flexible. When the reference clock in the synchronization network works normally, SETG synchronizes with the reference clock through the phase-locked loop, so that the equipment is in a network synchronization state; When the reference clock in the system fails or the clock transmission link fails, SETG uses the software to save the frequency information before the failure as its input reference, and it still keeps the network synchronization for a long time in exchange for the time to solve the fault. The clock signal is still provided to the next-level network element through the T4 phase-locked loop. Even in the worst case, the input reference clock is lost, but the phase-locked loop and its own VCO can work in free-running mode, but this mode is already very unstable.

6 Conclusion

In practical applications, this kind of synchronization application scheme is of great reference value. It can not only be used for synchronization of SDH networks, but for other digital networks, it can also be transplanted and used according to its network characteristics.

The Links:   TM25T3A-H NL12880BC20-32F

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