“The 3/3-phase dual-winding induction generator has two windings: the excitation compensation winding and the power winding, as shown in Figure 1. A power Electronic conversion device is connected to the excitation compensation winding to provide the reactive power required by the induction generator , So that a stable DC voltage is output on the power winding.
The 3/3-phase dual-winding induction generator has two windings: the excitation compensation winding and the power winding, as shown in Figure 1. A power electronic conversion device is connected to the excitation compensation winding to provide the reactive power required by the induction generator , So that a stable DC voltage is output on the power winding.
The meaning of each parameter in Figure 1 is as follows:
isa, isb, isc-the excitation current in the compensation winding;
usa, usb, usc-compensation winding phase voltage;
ipa, ipb, ipc-power winding current;
upa, upb, upc-power winding phase voltage;
Udc-output voltage on the DC side of the diode rectifier bridge;
uc――Voltage of the capacitor on the DC side of the converter.
The power electronic conversion device is composed of a power device, its drive circuit and a control circuit. The power device uses Mitsubishi’s Intelligent Power Module (IPM) PM75CSA120 (75A/1200V), and the drive circuit uses optocoupler HCPL4502. The control circuit is DSP+FPGA constitute.
Figure 2 Interface circuit of the control circuit
2､The interface circuit between EPM7128 and TMS320C32 and peripherals
Figure 2 shows the interface circuit of the control circuit. The DSP used in the control circuit is TMS320C32, which is the third-generation high-performance CMOS 32-bit digital signal processor produced by TI. It relies on a powerful instruction system and high-speed data processing capabilities. And innovative structure, it has become an ideal industrial control DSP device. Its main features are: a single-cycle instruction execution time of 50ns, with the ability to execute 22 million instructions per second and perform 40 million floating-point operations; provides An enhanced external memory configuration interface, with more flexible memory management and data processing methods. The FPGA device used in the control circuit is ALTERA’s EPM7128, which is a high-density and high-performance CMOS EPLD device, developed with ALTERA’s MAXPLUS II With system software, it can 100% imitate high-density TTL devices integrated with various logic functions and a variety of programmable logic. Using similar devices as DSP-specific peripheral integrated circuits ASIC is more economical and flexible, and can further reduce the control system cost.
A three-phase transformer is used for voltage detection, and an HL current sensor is used for current detection. The level conversion circuit is used to convert the detected signal to a level of 0~5V. The A/D converter is selected as ADS7862. The protection circuit is obtained by using a voltage comparator 311. Overvoltage/overcurrent fault signal.
DSP completes the following four tasks: data collection and processing, control algorithm completion, PWM pulse value calculation and protection interrupt processing.
FPGA completes the following three tasks: management of the interface between DSP and various external devices; pulse output and dead zone generation; protection signal processing. Figure 3 Interface between FPGA and A/D converter and DSP
3､Use FPGA to realize the high-speed interface between DSP and ADS7862
ADS7862 is an A/D converter specially designed for motor and power system control by TI. Its main features are: 4 fully differential input interfaces, which can be divided into two groups, and two channels can be converted at the same time; 12bits parallel output; each The conversion rate of the channel is 500kHz. The control method is: the value of the A0 line determines which two channels are converted; the conversion is initiated by a low-level pulse with a pulse width greater than 250ns on the Convst line; the low-level control of the CS and RD lines For data reading, two channels of data can be obtained by reading the signal twice in succession.
Two ADS7862s are used in the system, their control lines use the same interface, and the data lines are connected to the low 12 bits of the DSP’s high/low 16-bit data lines. In this way, the DSP can control two A/D converters at the same time. : 4 channels are converted at the same time; each read operation can get two channels of data.
As shown in Figure 3, the control signal of the A/D converter is mapped to the three external ports of the DSP: A0､ADCS (and ADRD uses one port) and CONVST. Use a logic decoder in the FPGA to decode the ports. The decoding program written in AHDL language is as follows:
Among them, 0 means low level, 1 means high level. RW=1 means read, RW=0 means write.
The DSP can control the A/D converter by operating these three ports: writing to the CONVST port can start the A/D converter; reading the ADCS port can read data from the A/D converter; writing data to the A0 port can be set Different channels. Using the above method can realize seamless and fast connection between DSP and A/D converter.
4､Use FPGA to realize PWM pulse generation and dead zone injection
In addition to managing the interface between DSP and peripherals, FPGA also completes the generation of PWM pulses and the injection of dead-zone. Integrating the PWM chip and dead-zone generator in the FPGA enables the DSP to focus on the implementation of complex algorithms, and the PWM The processing is handed over to the FPGA system to make the system run in a quasi-parallel processing state.
5､Use FPGA to realize system protection
In order to protect generators and IGBT power devices, the excitation control system provides multiple protection functions: converter DC side overvoltage protection; converter AC current overcurrent protection; converter overtemperature protection; generator output overvoltage protection ;IPM error protection. Figure 5 Voltage and current of excitation winding and system DC voltage waveform in steady state.
Use the hardware logic shown in Figure 4 to implement the protection function. When the FPGA detects the corresponding fault signal, the D flip-flop outputs an error signal, which makes the AND gate output a low level, which blocks all PWMs Pulse and trigger a DSP external interrupt signal. When the DSP responds to an external interrupt, you can use the PRO port to read the wrong status bit. The CLEAR port is used to clear the D flip-flop, so the system can be restarted.
Figure 5 shows the experimental waveform diagram of this control system: the output current of the converter is basically sinusoidal; the capacitor voltage on the converter side is stable at 365V; the output voltage on the power winding side is stable at 510V.