“This article will discuss how to evaluate the robustness of SiC MOSFETs under avalanche operating conditions. MOSFET power converters, especially electric vehicle drive motor power converters, need to be able to withstand certain operating conditions. If the device fails or the gate drive command signal is wrong during the freewheeling conduction period, it will cause the converter power switch tube to work under avalanche conditions. Therefore, this article simulates an avalanche event, performs a non-clamped inductive load switch test, and uses different SiC MOSFET devices to evaluate the failure energy and robustness of the technology according to different test conditions.
Author: Salvatore La Mantia1, Mario Pulvirenti2, Angelo G. Sciacca2, Massimo Nania2, STMicroelectronics
This article will discuss how to evaluate the robustness of SiC MOSFETs under avalanche operating conditions. MOSFET power converters, especially electric vehicle drive motor power converters, need to be able to withstand certain operating conditions. If the device fails or the gate drive command signal is wrong during the freewheeling conduction period, it will cause the converter power switch tube to work under avalanche conditions. Therefore, this article simulates an avalanche event, performs a non-clamped inductive load switch test, and uses different SiC MOSFET devices to evaluate the failure energy and robustness of the technology according to different test conditions.
Energy efficiency and reliability are the main characteristics necessary for all Electronic power converters.In application fields related to human social activities and ecological environmental protection, such as transportation, industry, energy conversion, etc., standard silicon-based power switches have been replaced by SiC MOSFETs, because SiC MOSFETs have advantages in current density/chip area, breakdown voltage, Better performance in terms of switching frequency and operating temperature, which can reduce the volume and size of the power converter while improving energy efficiency,.
Using the latest generation of SiC MOSFETs to design power converters should seriously consider the reliability and robustness of the devices, so as to avoid abnormal failure phenomena that damage the overall safety of the system,.Short circuit and avalanche are abnormal events that may cause serious failure of the switch tube of the power converter .
Short-circuit events may be caused by faulty and uncontrolled operating conditions, such as incorrect device switching sequence commands. When drain-source voltage VDSWhen the breakdown voltage rating is exceeded, an avalanche event will occur.
For dvDS/dt and diD/dt application with a high rate of change, during the switching transient, VDSThe breakdown voltage rating may be exceeded.The high transient rate combined with the inherent parasitic inductance of the converter layout will produce voltage spikes, and in extreme cases, lead to avalanche events.,,. SiC MOSFET may have these operating conditions, and the dv of discrete devicesDS/dt may easily exceed 100V/ns, diD/dt exceeds 10A/ns ,.
On the other hand, motor power converters are also a focus of attention. For example, the drive motor inverters of electric vehicles, industrial servo motors, etc. The loads of these applications have typical inductance characteristics, and power switches must also be equipped with freewheeling diodes. Function of.Therefore, when the diode is turned off, the rest of the devices will conduct the load current and perform the unclamped inductive load switch UIS operation. It is inevitable to work in the avalanche state.. During this kind of avalanche, in addition to very high overvoltage, high energy dissipation is also an important issue to consider, because the device must withstand abnormal voltage and current values.
It is necessary to use failure detection algorithms and protection systems to cooperate with converter design methods that are also based on “reliability” standards..However, in addition to safety protection and best design rules, power switches must also be robust, that is, “robust”, in order to withstand a certain degree of abnormal working conditions, because even ultra-fast detection algorithms and protection systems cannot Immediate effect. The avalanche problem of SiC MOSFET has become an important topic. As the technology is not yet fully mature, special research is needed.-.
The purpose of this article is to analyze the robustness of SiC MOSFETs under avalanche operating conditions. In order to verify the robustness analysis results, we have done many experiments. Finally, we introduced the robustness of the device under different UIS test conditions.
Generally speaking, an avalanche event only occurs when the device reaches the breakdown voltage. Under normal operating conditions, this phenomenon occurs in all applications that set or require high switching frequencies.
Taking the application based on the half-bridge converter as an example, let us explain the avalanche phenomenon in detail.
Figure 1 (a) is a simplified schematic diagram of the half-bridge converter circuit. There are two SiC MOSFET switch tubes in the circuit, each with QHAnd QLMeans that, in addition to the switch tube, there is an inductive load; Figure 1 (b) is the equivalent circuit diagram of the above circuit, the most important part is the main parasitic components, especially the equivalent parasitic inductance of the power circuit LDH, LSH, LDLAnd LSL, The power circuit refers to the connection + DC circuit (VDD) And QHDrain, QHSource to QLDrain, QLSource to the power rail of the DC circuit. In addition, LGH, LGLIs QHAnd QLThe equivalent parasitic inductance of the signal loop of the gate-source path.Considering that HiP247 packaged discrete devices have three or four leads, the parasitic inductance above includes the parasitic inductance of SiC MOSFET bonding wires and leads. For details, see,. It is also important to consider the parasitic capacitance C of the SiC MOSFETGS, CDSAnd CGD, These parameters are the drain-source voltage VDSThe function.
It is not difficult to understand the voltage spikes generated during the extreme operating conditions of the following two cases:
1) The active device is turned on, and the body diode of the passive device is turned off
2) The active device is turned off, and the body diode of the passive device is turned on
Use a 1200V, 25mΩ, HIP247-4L packaged SiC MOSFET discrete device, and do an experimental test according to the scheme in Figure 1 to describe under what circumstances transients are defined as extreme operating conditions. For simplicity, the QLAs an active device, it is controlled by a suitable gate driver circuit; QHIt is a passive device used as a freewheeling diode, and a constant negative gate-source voltage of -5V is usually applied to the relevant terminal.
Figure 1: Half-bridge converter leg: (a) Simplified block diagram, (b) Equivalent circuit including the main parasitic components.
By analyzing the experimental results in Figure 2, we can know the extreme working conditions of Case 1).
Figure 2: At 850V, 130A, QH When the body diode is off, VGS, ID And VDSTypical waveform.
This section focuses on the QLQ when onHThe “reverse recovery” process of the body diode. The test condition is 175°C, VDD=850V, ID=130A. The reverse recovery process of SiC MOSFET is an important topic, and many people are studying this phenomenon,. The soft recovery and hard recovery modes are affected by factors such as carrier lifetime, doping distribution, and die area. From an application point of view, the reverse recovery characteristic is mainly related to the magnitude of the forward current IDAnd its rate of change diD/dt is related to operating temperature. Figure 2 shows the I at a rate of change of 12A/nsDQ causedHBody diode hard recovery characteristics. Since the junction is depleted very quickly, the drain-source voltage VDSRise at the fastest speed. In diD/dt and dirrUnder the combined effect of /dt and parasitic inductance, the peak voltage phenomenon is serious, and theDSVibration behavior is seen on the waveform. In addition, VGSThe waveform oscillates obviously, the voltage should be clamped to avoid stray conduction.
Quick recovery is used to describe the effect of recovery, the concept definition is detailed in the literature.
By optimizing the layout of the converter circuit board, the parasitic inductance is reduced to a very low level, which can limit the voltage spikes generated during the turn-off period when the current rate of change is very high, so as to maximize the use of the performance of the SiC MOSFET.
The experimental test results in Figure 3 explain the extreme working conditions of Case 2). The picture shows Q at room temperature (25°C), 850V, 130ALRelevant parameter waveform at “off”. Because the device adopts HIP247-4L package, the gate resistance R of 3.3ΩgAccelerate the turn-off transient, and VDSThe peak value is very high (about 1550V).
Figure 3: Turn off Q at 850V, 130AL, VGS, ID, VDS And PoffTypical waveform.
By further reducing RgIncreasing the resistance value to turn off the speed will cause an avalanche event, but the avalanche state is not reached in this experimental report.
However, in addition to extreme operating conditions, component failure can also lead to avalanche events.
As an example of the half-bridge converter in Figure 1 mentioned earlier, when QHWhen the freewheeling diode fails, causing the device to turn off, the load current must flow through the complementary device Q during the turn-off transientL, This process is called non-clamped inductive load switch UIS. During this event, the device must withstand a certain level of energy until it reaches QLBreak through the limit value.
This failure mechanism is related to critical temperature and heat generation. SiC MOSFETs do not have other failure modes found on silicon-based devices, such as BJT latch. The avalanche energy test results under UIS conditions are used to define the robustness of SiC MOSFETs.
Fig. 4(a) and Fig. 4(b) are UIS test results of SiC MOSFET. These tests are in Figure 1 without QHIs done in the configuration, the test condition is VDD=100V, VGS=-5/18V, RGL=4,7Ω, L=50mH, Tc=25°C, the reason for this choice will be explained in detail in the next chapter.
Figure 4(a) shows the first three pulse tests. QLThe current is being conducted, and it is turned off at the first pulse, as shown in the blue VGS, VDSAnd IDAs shown in the waveform, there is an overvoltage, VDSSlightly lower than 1500V, but the device has no avalanche. After increasing the pulse period, as shown in the green waveform in the figure, the current IDAt 5A, the device begins to withstand avalanche voltage. Do the UIS test again, as shown by the black waveform, the current value becomes larger, but because the load Inductor is small, the failure energy is not reached until the current value is very large.
Figure 4: UIS experiment, (a) the waveform at the beginning of the avalanche process; (b) the waveform when the last two pulses are applied.
Figure 4(b) shows the test result of the last case. The blue waveform is the waveform generated by the penultimate pulse before the device fails after a series of single pulses. It can be seen from the figure that the device can handle the turn-off transient, and the tolerance is calculated according to the following avalanche energy formula (1) The avalanche energy of about 0,7J, the maximum drain current is 170A, and the average avalanche voltage is 1668V.
The red waveform is the failure waveform obtained when the last pulse is applied. At this time, the device can no longer withstand avalanche energy, and failure occurs at t*, and the drain current begins to increase suddenly.
Robustness evaluation and avalanche test
We used three sets of 1200V SiC MOSFE to do UIS testing. Table 1 lists the main data of these three sets of devices.
5(a) shows the test equivalent circuit diagram, and 5(b) shows the relevant experimental device. QLIt is the device under test (DUT), and the test goal is to analyze the turn-off characteristics of the DUT.
Table 1: SiC MOSFET specifications
Figure 5: UIS experimental device: (a) equivalent circuit, (b) experimental platform
Set A, B, C three test conditions; apply a single pulse sequence with increasing cycle until the device under test fails.
A. vs RGL=4,7Ω, 10Ω, 47Ω, at L=50uH, Tc=25°C
B. vs L=50uH, 1mH, at RGL=4,7Ω, Tc=25°C
C. vs Tc=25°C, 90°C, 200°C, at L=50uH, RGL=4,7Ω
In order to facilitate statistics, five samples were drawn from the three groups of devices D1, D2, and D3, and a UIS experiment was performed according to each test condition to measure and calculate the failure current and failure energy, see Figure 6, Figure 7, and Figure 8.
Fig. 6(a) shows a typical device extracted from SiC MOSFET D3, and the V of UIS test is done according to test condition “A”DS And IDFailure waveform.
Figure 6: UIS vs. RGFinal test result: (a) V of a D3 sampleDSAnd IDTypical value; (b) Average failure energy EAV.
For clarity, only R is givenG = Waveforms of 4.7Ω and 47Ω. We observe that the failure current is not affected by RGLImpact. Figure 6(b) shows the average E of the three groups D1, D2 and D3AV.
Notice EAVThe failure energy is slightly reduced and can be ignored. Therefore, it can be concluded that the robustness of these SiC MOSFETs is comparable to R under the UIS test conditions.GIrrelevant.
Figure 7 (a) and (b) show the failure waveforms of UIS test performed once at L=50mH and 1mH under test condition B. For simplicity, only a typical sample is taken from SiC MOSFET D3 for experiment .
After increasing the load inductance, the energy stored in the inductor increases, so the failure current decreases.
Figure 7: UIS’s final test result on L (a) When L=50mH, the V of D3 sampleDS And ID Typical value (b) When L=1mH, the V of D3 sampleDS And ID Typical value (c) Average failure energy EAV.
Figure 7(c) shows the average E of D1, D2 and D3AVIn relation to L, it can be observed that the failure energy E of device D3AVAs the load inductance increases, it increases significantly, while the E of D1 and D2AVThere is a slight increase. The reason for this behavior characteristic can be found by analyzing Figure 8. Figure 8 is the junction temperature T calculated according to equation (2)jDistribution map:
Among them: T0 is the starting temperature, PAVIs the average pulse power, ZthIt is the thermal resistance of the chip package. The TO247-3L package without a heat sink was used in this experiment.
The size of the stored energy of the inductor is related to the inductance value, and the stored energy will be applied to the die and converted into heat energy to be dissipated.
As shown in Figure 7(a), a low inductance value will cause a very large thermal transient. This is because the current reaches a very high value within a few microseconds, as shown in Figure 7(a). Therefore, the junction The temperature rises very fast during UIS, but the die does not have enough time to dissipate the heat. On the contrary, in the case of a high inductance value, the current value is lower, as shown in Figure 7(b), and the die has enough time to dissipate heat, so the temperature rises smoothly.
This experimental result explains why the E of the device under test D3AVThe reason for the significant increase with the increase of load inductance, in addition, its die area is larger than that of SiC MOSFET D1 and D2.
Figure 8: The estimated junction temperature Tj vs. L curve of a typical D3 device.
Finally, the UIS test results of test condition C are reported in Figure 9. Test condition C is a function of package temperature, and the package temperature value is measured with a thermocouple.
Figure 9(a) shows the V of D3 at three different temperatures: Tc=25°C, 90°C and 200°CDSAnd IDWaveform. Unsurprisingly, the trends of the three lines D1, D2 and D3 are similar. The higher the operating temperature, the E that causes device failure.AVThe lower, Figure 9(b).
Figure 9: UIS’s final test results on Tc; (a) V of D3 samples at different TcDSAnd IDTypical value; (b) Average failure energy EAV To TCcurve
This article discusses the operating conditions that may cause power devices to be in an avalanche state that need to be considered in SiC MOSFET applications. In order to evaluate the robustness of SiC MOSFETs, this paper evaluates the avalanche energy through experimental tests. Finally, three SiC MOSFETs with different characteristics are used for comparison tests to define the maximum avalanche energy that causes device failure. Avalanche energy is proportional to chip area and is a function of gate resistance, load inductance, and case temperature.
This kind of avalanche tolerance analysis on discrete devices has attracted great attention from designers who use power modules to develop applications, because power modules are composed of many parallel chips. The robustness of these chips needs to be highly consistent, and special tests must be carried out. analyze. In addition, for specific applications, such as automotive applications, to evaluate robustness under avalanche conditions, single pulse avalanche testing and repeated avalanche testing methods can be considered. This is a key subject and will be the target of the recent evaluation activities.
 F. Wang and Z. Zhang “Overview of Silicon Carbide Technology: Device, Converter, System, and Application,” Power Electr. And Appl. Trans on. CPSS, vol. 1, no. 1, pp. 13-32, December 2016.
 S. Ji, Z. Zhang, FF Wang “Overview of High Voltage SiC Power semiconductor Devices: Development and Application,” CES Trans. On Elec. Machines and Systems, vol. 1, no. 3, Sept. 2017, pp.: 254-264.
 B. Wang, J. Cai, X.Du and L. Zhou “Review of Power Semiconductor Device Reliability for Power Converters,” CPSS Trans. On Pow. Elect. and Appl. Vol.2, no.2, pp. 101- 117, June2017.
 A. Hanif, Y. Yu, D. DeVoto and F. Khan “A Comprehensive Review Toward the State-of-the-Art in Failure and Lifetime Predictions of Power Electronic Devices,” IEEE Trans. On Pow. Elect. vol.34 , no.5, pp. 4729- 4746May2019.
 B. Mirafzal “Survey of Fault-Tolerance Techniques for Three-Phase Voltage Source Inverters,” IEEE Trans. on Ind. Elec. Vol.61, no.10, pp. 5192-5202, Oct.2014.
 F. Richardeau, P. Baudesson, TA Meynard “Failures-Tolerance and Remedial Strategies of a PWM Multicell Inverter,” IEEE Trans. Power Elec., vol. 17, no. 6, pp 905-912, Nov. 2002.
 A. Fayyaz, G. Romano, J. Urresti, M. Riccio, A. Castellazzi, A. Irace, and N. Wright, “A Comprehensive Study on the Avalanche Breakdown Robustness of Silicon Carbide Power MOSFETs”, Energies, vol. 10 , no. 4, pp. 452-466, 2017.
 MD Kelley, BN Pushpakaran and Stephen B. Bayne “Single-Pulse Avalanche Mode Robustness of Commercial 1200 V/80 mΩ SiC MOSFETs,” IEEE Trans. On Pow. Elec. Vol. 32, no. 8, pp. 6405-6415, Aug. 2017.
 I. Dchar, M. Zolkos, C. Buttay, H. Morel “Robustness of SiC MOSFET under Avalanche Conditions”, 2017 IEEE Applied Power Electronics Conference and Exposition (APEC)
 N. Ren, H. Hu, KL Wang, Z. Zuo, R. Li, K. Sheng “Investigation on Single Pulse Avalanche Failure of 900V SiC MOSFETs” Int. Symp. On Power Semic. Dev. & ICs, May 13- 17, 2018.
 J. Wei, S. Liu, S. Li, J. Fang, T. Li, and W. Sun “Comprehensive Investigations on Degradations of Dynamic Characteristics for SiC Power MOSFETs under Repetitive Avalanche Shocks,” IEEE Trans. on Power Elec. Vol .: 34, no: 3, pp. 2748C 2757, March 2019
 J. Hu, O. Alatise, J. Angel Ortiz Gonzalez, R. Bonyadi, P. Alexakis, L. Ran and P. Mawby “Robustness and Balancing of Parallel-Connected Power Devices: SiC Versus CoolMOS,” IEEE Trans. On Ind . Elec. Vol. 63, no.4, pp.2092-2102 April 2016.
 M. Nawaz “Evaluation of SiC MOSFET power modules under unclamped inductive switching test environment”, Journal of Microelec. Reliability, vol. 63, pp. 97-103, 2016.
 H. Chen, D. Divan “High Speed Switching Issues of High Power Rated Silicon-Carbide Devices and the Mitigation Methods” 2015 ECCE, pp. 2254-2260.
 M. Pulvirenti, L. Salvo, G. Scelba, AG Sciacca, M. Nania, G. Scarcella, M. Cacciato, “Characterization and Modeling of SiC MOSFETs Turn On in a Half Bridge Converter” 2019 IEEE En. Conv. Cong. and Expo. (ECCE2019).
 M. Pulvirenti, G. Monotoro, M. Nania, R. Scollo, G. Scelba, M. Cacciato, G. Scarcella, L. Salvo “Analysis of Transient Gate-Source OverVoltages in Silicon Carbide MOSFET Power Devices” 2018 IEEE En. Conv. Cong. and Expo. (ECCE2018).
 J. Mari, F. Carastro, M.-J. Kell, P. Losee, T. Zoels “Diode snappiness from a user’s perspective” 2015, 17th European Conference on Power Electronics and Applications (EPE’15 ECCE-Europe).
 R. Wu, F. Blaabjerg, H. Wang, M. Liserre, “Overview of catastrophic failures of freewheeling diodes in power electronic circuits”, Microelectronics Reliability, vol. 53, no.9-11, 2013, pp.:1788- 1792.
 Y. Shi, R. Xie, L. Wang, Y. Shi, and H. Li, “Switching Characterization and Short-Circuit Protection of 1200V SiC MOSFET T-Type Module in PV Inverter Application”, IEEE Trans. on Ind. Electron ., to be published.
 R. Katebi, J.He, N. Weise “An Advanced Three-Level Active Neutral-Point-Clamped Converter With Improved Fault-Tolerant Capabilities,” IEEE Trans. On Power Elect., vol. 33, no. 8, pp. 6897-6909, Aug. 2018.