“In this “Power Supply Design Tips”, we will study how to compromise conduction power consumption in a synchronous step-down power stage, which is related to the duty cycle and FET resistance ratio. Performing this trade-off process can result in a very useful starting point for FET selection. Usually, as an integral part of the design process, you will have a set of specifications that include the input voltage range and expected output voltage, and you need to select some FETs.

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Author: Robert Kollman

In this “Power Supply Design Tips”, we will study how to compromise conduction power consumption in a synchronous step-down power stage, which is related to the duty cycle and FET resistance ratio. Performing this trade-off process can result in a very useful starting point for FET selection. Usually, as an integral part of the design process, you will have a set of specifications that include the input voltage range and expected output voltage, and you need to select some FETs. In addition, if you are an IC designer, you will also have a certain budget, which stipulates the FET cost or package size. These two inputs will help you choose the total MOSFET chip area. Later, these inputs can be used to optimize the efficiency of each FET area.

Figure 1 Conduction loss is related to FET resistance ratio and duty cycle

First, FET resistance is inversely proportional to its area. Therefore, if you allocate a certain total area to the FET, and you make the high-side area larger (in order to reduce its resistance), the area of the low-side must decrease and its resistance increases. Second, the percentage of high-side and low-side FET conduction time is related to V_{OUT}/V_{IN }The conversion ratio of is related, which is first equal to the high-side duty cycle (D). The high-side FET is turned on for D percentage time, and the remaining (1-D) percentage time is turned on by the low-side FET. Figure 1 shows the standardized conduction loss, which is related to the percentage of FET area dedicated to the high-side FET (X-axis) and the conversion factor (curve). Obviously, under a certain set conversion ratio condition, the best chip area distribution can be achieved between the high side and the low side, and the total conduction loss is the smallest at this time. Under low conversion ratio conditions, please use a smaller high-side FET. Conversely, when the conversion ratio is high, use more FETs on the top. The area allocation is very important, because if the output is increased to 3.6V, the circuit optimized for the 12V:1.2V conversion ratio (10% duty cycle) will increase its conduction loss by 30%, and if the output is further increased to 6V, The conduction loss will increase by nearly 80%. Finally, it should be pointed out that all the curves pass through the same point when 50% of the high side area is allocated. This is because the resistances of the two FETs are equal at this point.

Figure 2 There is an optimal area ratio based on the conversion ratio

**Note: The resistance ratio is inversely proportional to the area ratio**

From Figure 1, we know that the best conduction loss extreme occurs at a 50% conversion ratio. However, under other conversion ratio conditions, the loss can be reduced below this level. Appendix 1 gives the mathematical calculation method for this optimization, and Figure 2 shows the calculation result. Even at extremely low conversion ratios, a large part of the FET chip area should be used for high-side FETs. The same is true for high conversion ratios; a large part of the area should be used for the low side. These results are preliminary studies on this issue. They do not include various specific resistance values between high-side and low-side FETs, the effect of switching speed, or the cost and resistance associated with packaging this chip area. Many aspects. However, it provides a good starting point for determining the resistance ratio between FETs, and should achieve a better overall compromise in FET selection.

Next time, we will discuss how to determine the leakage inductance requirements of the coupled Inductor used by SEPIC, so stay tuned.

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