“The chip industry has realized that the process of shrinking according to Moore’s Law has slowed down, and the industry seems unwilling to face the imminent great changes in chip design ─ ─ transformation from process to packaging technology.
The chip industry has realized that the process of shrinking according to Moore’s Law has slowed down, and the industry seems unwilling to face the imminent great changes in chip design ─ ─ transformation from process to packaging technology.
An important trend in consumer electronics and mobile communication devices is toward more compactness and portability. Today’s users demand more functionality, higher performance, higher speed and smaller form factor solutions; while software systems and billions of connected devices are rapidly forming a vast Internet of Things (IoT).
All of these forces are driving semiconductor companies to develop new advanced integrated circuit (IC) packaging technologies to provide higher levels of silicon integration in increasingly miniaturized packages. The past decade has seen the emergence of new packaging technologies such as fan-out wafer-level packaging (FOWLP), stacked IC packaging, and complex system in package (SiP), as well as packaging substrates, flip-chip interconnects, and silicon Through holes, etc., the technological progress is obvious.
All these advancements have resulted in a significant increase in IC packaging density and opened up new opportunities for the development of Electronic products. Let’s take a look at the latest technologies and market trends in the IC packaging industry, and what the most advanced packaging and solutions mean for developing cutting-edge products and staying ahead of the technology.
Packaging is tied to Moore’s Law
Moore’s Law is a successful empirical prediction that simply doubles the density of transistors in ICs every two years. Mainly due to the slowing down of gate length shrinkage, the integration density of transistors is limited at 2D, so people start to continue to push integration density with 3D. One example is stacked memory as a 3D chip, where multiple layers of the same technology are stacked together, further increasing the integration density.
Why chip manufacturing has been pursuing advanced IC packaging? One prominent purpose is to “beyond Moore’s Law (Moore than Moore).” When chip scaling became more difficult and expensive at each node, engineers had to put multiple chips into advanced packages as an alternative to chip scaling.
For decades, semiconductor processing technology has steadily reduced feature sizes from tens of microns to nanometers, effectively doubling component density every 18 months. At the same time, however, design and manufacturing costs have risen, critical profit margins have narrowed, and many other challenges appear to be holding back further progress. In addition, the increased density of transistors in a single chip creates problems when connecting chips together, such as limiting the number of I/O pins and the speed of chip-to-chip interconnects.
These limitations have proven particularly problematic in applications such as artificial intelligence (AI) edge and cloud systems that require large amounts of high-bandwidth memory. To address these issues and continue to increase component density, the industry has developed several advanced packaging technologies that interconnect multiple chips in a compact, high-performance package that operates as a single component on a board.
Market Demands Advanced IC Packaging
For many applications, Moore’s Law is no longer cost-effective, especially for the integration of heterogeneous functions. “More than Moore”, such as Multi-Chip Modules (MCM) and SiPs have emerged as alternatives for integrating large amounts of logic and memory, analog, MEMS, etc. into (sub)system solutions. However, these methods were and are client-specific and require significant development time and cost.
The so-called “beyond molar” refers to the increase in functional density, that is, the integration of multiple technologies into a composite device. This may include stacking of chips and/or packages; the use of multiple semiconductor materials and various electronic routing technologies such as ball grid array (BGA), through silicon vias (TSV), interlayers and wire bonding. A More than Moore device can integrate logic, memory, sensors and antennas from different front-end manufacturing nodes into a single package through heterogeneous integration.
There are many ways to “beyond Moore” with advanced IC packaging, but here are a few key techniques.
The popularity of SiP ensures IoT growth
Many see IoT as the third wave of technology, the PC boom of the late 1980s and early 90s as the first wave, and mobile phones as the second. In the third wave, engineers build on the experience and foundation of the previous two waves, making the daily chores more closely connected.
Market research firm Strategy Analytics estimates that by 2023, the global IoT market represented by smart homes will reach US$157 billion, with obvious opportunities for semiconductor growth, and packaging technology will play a role in fueling future system development.
According to Vik Chaudhry, senior director of product marketing and business development at Amkor Technology, the explosion of IoT has driven the popularity of SiP packaging, making it a popular way to integrate IoT solutions because it provides manufacturers with the opportunity to combine different technology, and reduce costs by using “off-the-shelf” components. The size of IoT solutions can also be reduced through integrated packaging, further reducing costs.
He explained: “IoT packaging requires low cost, good power consumption (low power silicon part) and support for multiple RF standards (such as BTLE, Wi-Fi or ZigBee), and the package has good RF shielding. When using sensors Cavity-based solutions are popular, especially when there are perceptual delivery requirements, such as microphones. IoT packages must also be production-ready, and waiting for new custom packages is often not feasible due to time-to-market constraints. Whether the solution is discrete or integrated, the footprint must be small.”
For IoT applications, SiP is the perfect way to integrate sensors, embedded processors and RF connectivity into a small form factor, known as sensor fusion, and it also gives manufacturers an opportunity to quickly combine different technologies , without spending a lot of money on new mask sets. In addition to fast time-to-market, the SiP approach allows manufacturers to build solutions using off-the-shelf components, since all building blocks are already present in product form, so it is easy for engineers to rearrange the combinations to gain access to aspects such as antenna position, power consumption, etc. the best performance; can also take advantage of package integration to reduce the size of IoT solutions by 40%.
The advantages of SiP technology are:
Fusion of multiple technologies
Ability to integrate multiple technologies and components, such as combined MEMS and CMOS, in one package. This combination is not possible with conventional ICs. While MEMS and CMOS devices share many similarities, there are also some key differences. First, there is a need for a way to transmit perception to MEMS devices because they must interact with the environment; second, MEMS devices scale differently than CMOS different processes.
Using a variety of processes
The integration offered by SiP technology is particularly valuable for applications such as wearables, smart lights or smart homes, where space and size are critical. From the practical application point of view, the SiP design scheme integrates wafer-level packaging (WLP), 2.5D or 3D structure, flip-chip (flip-chip), wire bonding, package-on-package, etc. process; passive components, conformal shields, filters and antennas can also be embedded.
Several SiP packages for typical IoT scenarios
Fusion MEMS Sensors
MEMS sensors need to interact with the environment for sound, light or gas detection. The use of MEMS packaging typically involves migrating from QFN packaging to laminate-based packaging. Laminate designs can be either cavity-based or hybrid cavity packages, where one half of the package is molded and the other half provides a cavity for the MEMS device. This molded device is more able to withstand harsh environments.
Implement IoT standardized packaging
Currently, packaging designs for MEMS, sensors, and IoT devices are fragmented. Designers want to reuse the same footprints for multiple projects, even if those footprints are not always compatible with a specific application. Standardization of MEMS and sensor packaging will help reduce costs and accelerate MEMS adoption, increasing manufacturers’ confidence in bringing new products to market.
FOWLP for extreme performance
Moore’s Law seems to have come to an end in process technology, so advanced packaging technologies such as Fan-Out Wafer Level Packaging (FOWLP) can increase component density and performance and help address chip I/O constraints. The key to success, though, is to start with chip design.
Now, FOWLP has been used in the mass production of mobile devices. Its packaging process involves mounting individual chips on an interlayer substrate called a redistribution layer (RDL), which provides interconnects between chips and connections to I/O pads, all packaged in a molded Forming.
The so-called fan-out package is to fan out the connectors to the surface of the chip to achieve more external I/O, and use epoxy molding compound to completely embed the chip (die), so no wafer ball mounting, flux, flip chip is required. Process flows such as assembly, cleaning, underfill injection and curing. This in turn eliminates the middle layer and makes the implementation of heterogeneous integration simpler.
Fan-out technology can provide small footprint packages with more I/Os than other package types. As early as 2016, Apple integrated its 16nm A10 application processor and mobile DRAM into a package inside the iPhone 7 with the integrated fan-out (InFO) wafer-level packaging technology of TSMC. Provides better thermal management for application processors. TSMC’s InFO enables Apple to achieve a very thin package stack (PoP, Package-on-Package).
TSMC’s InFO Technology
The redistribution layer technology of the InFO platform connects the silicon die directly to the PCB layer without the need for another substrate. Through interconnect vias (TIVs) designed by TSMC can provide pillars that connect different silicon dies or components using a mix of vertical and horizontal interconnect technologies. InFO embodies the connection between its short vertical and long horizontal connections, accelerating the dissemination of information.
As an improvement to WLP, FOWLP technology can provide more external contacts with the silicon chip. It embeds the chip in an epoxy molding compound, and then creates a high-density RDL and solder balls on the wafer surface to form a reconstituted wafer.
Typically, it first dices a previously processed wafer into individual dies, then separates the dies on a carrier structure whose voids are filled to form a reconstituted wafer. FOWLP provides numerous connections between the package and the application board. In addition, the substrate is basically larger than the chip, so the chip spacing is more relaxed.
Traditional Multichip Packaging and FOWLP
There are several variants of FOWLP, each using slightly different manufacturing steps. FOWLP assemblies can be created using a mold-first process with die face-down or face-up mounting, or using RDL-first assemblies.
Molding priority method
The die is attached to the carrier using a temporary adhesive layer or thermal release layer, which is then molded into the package. If the die is mounted face down, the next steps are to release the temporary layer, connect the RDL, and form the solder balls that complete the package. If the die is mounted face up, some additional steps are required.
First, the individual die I/O connections must be expanded by adding copper pillars on them, and then overmolded. After molding, the backside of the fillet must be grounded to expose the post before connecting the RDL and forming the solder balls.
The RDL is attached to the carrier using a temporary release layer, while the die is attached to the RDL. Then comes assembly molding, carrier release, and solder ball molding. The final step in both methods is to separate the components so that they form a single device as a whole.
Two methods of FOWLP technique
These methods have different cost and performance tradeoffs. In terms of cost, the molding-preferred face-down method avoids making copper pillars and grinding, so the manufacturing cost is lower; it is most suitable for applications with low I/O counts; however, there are problems such as die shift, wafer warpage, etc. Limited application in complex multi-chip packages.
The face-up approach reduces these problems and offers advantages in thermal management, as the backside of the chip is fully exposed, facilitating heat dissipation.
In terms of performance, the connection path of the face-down method is shorter compared to the other two methods. Both methods have copper pillars that extend the connection to the RDL, and a layer of material under the chip that increases the parasitic capacitance between the connections, which affects its high-frequency performance.
2. The key to 5D to 3D IC packaging is TSV
In a 2.5D package, the chips are stacked or placed side-by-side on top of a through-silicon-via (TSV)-based interlayer. The middle layer at the bottom provides the connection between the chips. 2.5D packaging technology is an advancement of traditional 2D IC packaging technology, which enables finer traces and spaces.
2.5D packages are typically used in high-end ASICs, FPGAs, GPUs, and memory. In 2008, Xilinx split its large FPGA into four smaller, higher-yield chips and connected the chips to a silicon interlayer, giving birth to the 2.5D package that eventually became popular for high-bandwidth memory ( HBM) processor integration.
A fully functional 3D package of TSV connections
In 3D IC packaging, logic dies are stacked together, with vertical interconnections between silicon dies via copper TSVs, and active interlayers to connect dies. Unlike 2.5D, where components are stacked on an interlayer through conductive bumps or TSVs, 3D IC packaging uses multiple layers of silicon wafers and stacks components together through TSVs.
TSV is a key technology in 2.5D and 3D packaging solutions, which provides a vertical interconnect through the die silicon wafer. This package is fabricated in wafer form and filled with copper. A TSV is a long through-hole electrical connection that extends through the entire thickness of the chip or substrate, creating the shortest path from one side of the chip to the other. However, in addition to its own significant electrical properties, TSVs also have indirect effects on the electrical behavior of their nearby devices and interconnects.
To accurately simulate a 2.5D/3D heterogeneous system, designers need tools to extract precise electrical parameters from the physical structure of these 2.5D/3D elements, and then input these parameters into a behavioral simulator. Using 3D digital twins of complete component assemblies, designers can accurately extract parasitics in 2.5D and 3D models to analyze performance and proper protocol compliance.
It is worth noting that both 2.5D and 3D stacking generate various occasional physical stresses, such as those caused by substrate warpage and impact during mounting. Designers must be able to analyze the stress caused by this chip-package interaction and its effect on device performance. Once the package is nearly complete, an accurate 3D package thermal model needs to be exported for use in detailed PCB and system-wide thermal analysis to make final adjustments to the system enclosure and optimize natural and/or forced cooling.
Thermal Simulation of 3D IC Packages
Die adds icing on the cake for 3D IC packaging
There is also a 3D IC package using chiplets, which was invented by AMD, and is being studied by TSMC, Intel, and Huawei HiSilicon. It enables heterogeneous integration of CMOS and non-CMOS devices, perhaps helping to keep Moore’s Law going. The idea is to break down a large SoC into smaller dies to improve yield and reduce cost, while improving reusability for customers. Core-grain mode allows designers to build chips like building blocks, leveraging a variety of IP regardless of which node or technology they are made with; they can be built on a variety of materials, including silicon, glass, and laminate.
Core particles are expected to continue Moore’s Law
Next-generation IC designers must understand packaging
Arijit Raychowdhury, a professor at Georgia Tech and an expert in VLSI digital and mixed-signal design, said the new frontier in advanced IC design is packaging.
“Packaging is something that a design engineer has to understand,” he said. The focus of advanced IC design has shifted from process technology to packaging technology, but the problem is that “the industry doesn’t know enough about how this shift will progress.” He sees TSMC as a company in Companies that perform better in this regard.
He pointed out: “The chip industry has realized that the speed of process scaling in accordance with Moore’s Law has slowed down, and the industry seems to be reluctant to face the imminent change in chip design – the transition from process to packaging technology.”
Now, transistor scaling is close to the limit, but from a technical point of view, maybe scaling is not evolving as fast as we think. Taking memory manufacturing technology or back-end process transistor technology as an example, he believes that there will be many new things emerging, and the industry should act quickly in this specific field to discuss the “black magic” in this area.
Are you ready to face the technological evolution and challenges of packaging?