How to use the phase noise graph direction clock device characteristics and applicable application scenarios

Every few years, almost all high-frequency serial communication standards (PCI-Express, USB, Ethernet, Synchronous Optical Network (SONET), Serial ATA (SATA), Infiniband, etc.) that are widely used in the market will be revised to Better respond to the higher expectations of today’s data-hungry society.

Author: ON semiconductor Brijesh Shah

Every few years, almost all high-frequency serial communication standards (PCI-Express, USB, Ethernet, Synchronous Optical Network (SONET), Serial ATA (SATA), Infiniband, etc.) that are widely used in the market will be revised to Better respond to the higher expectations of today’s data-hungry society. With the introduction of new versions of these standards, the market’s demand for Electronic circuits that support them has intensified. High-performance clock generation and distribution devices integrated in contemporary system applications use frequency domain parameters, that is, phase noise and phase jitter to describe their performance. This article discusses how the phase noise diagram can be used to estimate the characteristics of clock devices not explicitly mentioned on the manufacturer’s data sheet, so that engineers can better judge the suitability for a specific application.

When applying high-speed serial links, period jitter can be used to derive the relative bit error rate (BER). The jitter transfer and PLL bandwidth of the clock device are also important metrics, because through these parameters, it is possible to better predict how the input source or input clock will affect the output of the device. All of these will help engineers choose the appropriate clock device that meets their needs. However, these parameters are rarely indicated directly, so calculations must be made.

Jitter transfer

Jitter transfer reveals the amount of attenuation or noise generated within a certain offset frequency range. It is determined by the loop filter response of the phase-locked loop (PLL). The phase noise map provides the noise density at all offset frequencies, so it contains the data necessary to determine the jitter transfer of the clock device. The best way to Display the transfer, generation, and attenuation of jitter is to use a clock source that has a higher noise floor at a lower offset frequency and a lower noise floor at a higher offset frequency. At low frequencies, the PLL will pass high-source noise to the output; at high frequencies, it will show an inherent noise floor, which is due to the low-pass bandwidth characteristics of the PLL.

Low-bandwidth PLL can attenuate jitter even at lower offset frequencies. The lower the PLL bandwidth, the higher the attenuation performance at these frequencies. However, the low-bandwidth PLL has the disadvantage of a slower response time-it will take time to track changes in the input clock. Most network communication links have less stringent constraints at lower offset frequencies.

PLL bandwidth

If an appropriate reference clock source is used, in addition to jitter transfer, the phase noise graph can also help determine the PLL bandwidth. In order to fully understand PLL bandwidth estimation and PLL jitter transfer, a simple measurement setup should be made, using two different clock sources to feed a high-performance zero-delay buffer (ZDB).

How to use the phase noise graph direction clock device characteristics and applicable application scenarios
Figure 1: Circuit diagram showing PLL bandwidth and jitter transfer measurement

Figure 1 shows a simple circuit diagram that describes the phase noise measurement setup. The measurement was performed using an Agilent 5052A signal source analyzer. Source 1 (high-performance clock generator) and ZDB are powered by a low-noise power supply.

How to use the phase noise graph direction clock device characteristics and applicable application scenarios
Figure 2: Phase noise diagram of source 1 and buffer output

As shown in Figure 2, the root mean square (RMS) phase jitter of source 1 is about 447 fs, while the buffer output is about 448.8 fs. RMS jitter is measured in an offset frequency range from 10 kHz to 20 MHz. At lower offset frequencies of 10 to 100 Hz, the buffer noise is higher compared to the source, but this is not a problem for most communication channels because it is easily tracked by the PLL. The output buffer phase noise figure roughly matches the source phase noise figure up to 1 MHz. Above this frequency, the bottom noise of the buffer output is lower than the bottom noise of the source, as shown in the second circle in Figure 2.

Source 2 uses a data pattern generator (DPG). It has a much higher noise floor than source 1. Therefore, the output diagram of the buffer shown in Figure 3 matches the input source at a lower frequency (10-100Hz). The buffer-PLL transmits input noise below 1 MHz; the abrupt changes around 30 kHz in the source noise graph are reflected in the buffer output noise graph, as shown in the first circle in Figure 3. For frequencies higher than 1 MHz, the buffer noise floor is significantly lower than the source noise floor, as shown in circle 2 in Figure 3; this means that the buffer acts as a jitter attenuator in this frequency range.

How to use the phase noise graph direction clock device characteristics and applicable application scenarios
Figure 3: Phase noise diagram of source 2 and buffered output

Period jitter

As mentioned earlier, period jitter is an important parameter used to approximate BER in high-speed serial standards, but usually clock device manufacturers only provide phase jitter or phase noise measured with low-noise frequency domain equipment data. The phase noise spectrum is defined as the attenuation (in dB/Hz) based on the peak of the carrier power spectral density. The relationship between phase noise spectral density and RMS period jitter is:

How to use the phase noise graph direction clock device characteristics and applicable application scenarios

In order to estimate the period jitter from the phase noise map, the phase noise of the offset frequency must be multiplied by the 〖4sin〗^2 (πfτ) function. The dB conversion 4〖sin〗^2 (πfτ) shows that it has a slope of -20dB/decade (see Figure 5). 4〖sin〗^2 (πfτ) The value in dB can be added to the phase noise graph data, and the unit is dBc. The numerical integration of the final data within the relevant offset frequency range will provide the phase noise density of the single sideband. For example, in order to estimate the period jitter based on the phase noise diagram given in Figure 4, add 4 〖sin〗^2 (πfτ) function data in dB to the phase noise (PN) data (in dBc/Hz) , As shown in Figure 5. The obtained blue curve shows the phase noise spectral density.

How to use the phase noise graph direction clock device characteristics and applicable application scenarios
Figure 4: The output phase noise diagram of the clock generator with glitches

Integrating the area below the blue curve in Figure 5 will get the phase noise spectral density (in dB) (corresponding to area A). It can be converted to root mean square pull using the following equation:

How to use the phase noise graph direction clock device characteristics and applicable application scenarios
Figure 6: RMS jitter conversion of phase noise

As shown in Figure 6, the area under the curve can be divided into several different parts (A1, A2, etc.) according to the shape of the curve or the use of a piecewise linear function. Since the noise at the lower offset frequency does not significantly affect the period jitter, only the curve at the higher offset frequency is considered. In order to improve the accuracy, the complete curve can be divided into multiple parts, corresponding to the influence of each part on the period jitter. The curve in Figure 6 is divided into 4 parts, and each part contains 2 relevant data points (phase noise, offset frequency). Using these data points, the area of ​​each part can be converted to equivalent jitter (expressed in seconds).

The contribution of each part to RMS jitter is shown in Figure 6. The sum of these RMS jitter values ​​can be calculated using the following equation:

How to use the phase noise graph direction clock device characteristics and applicable application scenarios

According to this equation, the total contribution of the four regions shown in Figure 6 to the jitter can be calculated to be 434 fs. This value is multiplied by 2 to get the total noise contribution (△trmsPN)-868 fs. In addition, there are two glitches in Figure 6. Since these glitches are at a single frequency, the following equations can be used to separately calculate and increase their contribution to jitter:

How to use the phase noise graph direction clock device characteristics and applicable application scenarios

The dB value of each glitch can be converted to jitter using Equation 3.

The example shown in Figure 6 has glitches at 1.4 MHz and 25 MHz, which are -111 dB and -72.6 dB, respectively. The equivalent RMS jitter of a 1.4 MHz glitch is 6.3 fs, and the equivalent RMS jitter of a 25 MHz glitch is 527 fs. Higher frequency glitches have a greater impact on period jitter than lower frequency glitches. The value of the 25 MHz glitch is much higher than the 1.4 MHz glitch. The total glitch RMS jitter value (△trms Spur) calculated using Equation 5 is very close to 527 fs, so the impact of 1.4 MHz glitches is negligible. High-dB glitches may be errors that are prone to occur due to increased jitter effects in some applications. Using Equation 2, the total period jitter of the graph depicted in Figure 6 can be estimated to be 1.015ps.

All in all, when engineers specify clock devices, frequency domain parameters such as phase noise and phase jitter are extremely valuable to them. The phase noise diagram provided by the device manufacturer is a very important performance indicator tool for these products. The graph can be used to approximate the bandwidth and jitter transfer characteristics of the PLL, thereby helping to determine its characteristics in the relevant frequency range (as a jitter attenuator or generator). It is also possible to estimate the period jitter based on a given graph by considering the phase noise in the dominant frequency range and the glitch at the critical frequency. Engineers seeking to specify clock devices for next-generation design applications can use this information to make more authoritative product modeling decisions.

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