Embracing the era of big data, interpreting 5G communication clock synchronization technology

With the advent of the era of big data, cloud computing and the Internet of Things, communication systems have evolved from a centralized system to a distributed system. In a centralized system, all processes or modules obtain time from the unique global clock of the system. The two events have a clear sequence.

Author: Wofle Yu

Preface

With the advent of the era of big data, cloud computing and the Internet of Things, communication systems have evolved from a centralized system to a distributed system. In a centralized system, all processes or modules obtain time from the unique global clock of the system. The two events have a clear sequence.

In a distributed system, the system cannot provide a unified global clock for modules that are independent of each other. Because the timing rates and operating environments of these local clocks are inconsistent, these local clocks will also appear inconsistent after a period of time. In order for these local clocks to reach the same time value again, a time synchronization operation must be performed.

Wolfe Yu, an engineer from Excelpoint Shijian, a technical authorized agent, explained the relevant knowledge of 5G communication clock synchronization.

Clock synchronization technology

The synchronization of each clock in the system requires comparing the difference between each clock and the system standard clock, and correcting the relative drift. For example, in GPS navigation system user equipment, we generally synchronize the clock by adjusting the time when the leading edge of the 1PPS signal appears. There is another kind of clock synchronization through the clock recovery technology of Ethernet. This technology is called Synchronous Ethernet Technology, or SyncE. Of course, there are other technologies, such as transmitting time information through radio waves, but these transmission methods can only achieve co-frequency transmission.

In order to achieve higher precision requirements, someone proposed a PTP transmission method. Later, with the continuous improvement of 5G technology, a combination of SyncE+PTP was proposed.

Embracing the era of big data, interpreting 5G communication clock synchronization technology

GPS clock synchronization

GPS synchronization three-dimensional coordinate theory

The GPS system uses working satellites to determine the three-dimensional coordinates of the receiver and obtains the clock deviation of the receiver to perform timing. In theory, as long as 4 or more working satellites are received, they can be accurately positioned and timed through the three-dimensional spatial coordinate formula. The coordinate theory is as shown in the figure below, and the specific derivation process will not be repeated.

Embracing the era of big data, interpreting 5G communication clock synchronization technology

Principle of GPS High Frequency Synthesizer System

In 2004, Nicholls and Carleton proposed the famous N/C system. The core technology of the N/C system is to use a 10MHz OCXO to simultaneously connect a frequency divider and a frequency multiplier to generate 1pps and 160MHz signals, respectively. Phase loop, real-time correction of OCXO output frequency.

Embracing the era of big data, interpreting 5G communication clock synchronization technology

In order to facilitate intuitive analysis, we reconstruct the system, the GPS receiver generates 1PPS output signal, and the 10MHz frequency division output 1PPS signal generated by OCXO, and then detects the phase offset through the signal of 10MHz frequency multiplied by 160MHz to achieve synchronization.

Embracing the era of big data, interpreting 5G communication clock synchronization technology

The essence of synchronization is to adjust the frequency and phase through the phase-locked loop. The digital phase-locked loop DPLL has strong tolerance to digital circuit noise, fast capture time, easy integration, and can provide complex processing algorithms.

The digital phase-locked loop mainly includes phase detector, digital loop filter, phase accumulator, DA conversion, etc. The phase detector compares the local estimated signal with the input signal to generate a corresponding phase error sequence. After loop filtering, the phase control word is generated and the phase is adjusted. At the same time, the frequency control word adjusts the frequency output.

Embracing the era of big data, interpreting 5G communication clock synchronization technology

At present, most phase-locked loops adopt a structure based on DDS+PLL, which realizes fast lock phase and frequency by calculating the frequency control word and phase control word respectively to make adjustments.

SyncE clock synchronization

SyncE (Synchronous Ethernet) architecture

Synchronous Ethernet technology is a technology that uses the Ethernet link code stream to recover the clock frequency, referred to as SyncE. It uses a high-precision clock at the Ethernet source end and uses the existing Ethernet physical layer interface PHY to send data. The clock frequency is recovered and extracted through CDR to maintain high-precision clock performance. The SyncE technology block diagram is as follows:

Embracing the era of big data, interpreting 5G communication clock synchronization technology

The basic principle of CDR (clock data recovery)

The Ethernet PHY layer transmits the NRZ code stream. On the transmission side, the code stream is re-encoded into 4B/5B, 8B/10B, 64B/66B codes, and clock and data recovery can be completed through CDR (clock data recovery).

Embracing the era of big data, interpreting 5G communication clock synchronization technology

The principle of CDR is roughly as follows: the frequency detection loop Coarse Loop completes frequency capture, and the phase detection loop Fine Loop adjusts the relationship between the phase and recovers the clock, and restores the data signal.

Embracing the era of big data, interpreting 5G communication clock synchronization technology

The CDR circuit is mainly divided into:

• Dual-loop structure CDR, composed of a phase-locked loop and a delay-locked loop, the phase-locked loop provides a low-jitter quadrature clock of the required frequency, and the phase-locked loop adjusts the phase of the quadrature clock to the best sampling phase;

• Fully digital CDR, this circuit adopts all digital circuit to realize through oversampling method, the power consumption is low, but the accuracy is limited;

• There is also a non-reference clock CDR. This circuit does not need to provide an off-chip reference clock, which is flexible in application, but has a small operating frequency range.

SyncE exhibits an excellent frequency tracking effect in clock synchronization, but SyncE cannot judge the transmission delay of the clock signal on the line in clock transmission.

Precision time protocol (PTP) evolution

Network time protocol NTP (Network time protocol) theory

PTP evolved from NTP. Let’s talk about the NTP network protocol first. The slave clock sends a message packet to the master clock and records the slave timestamp T1 when the message packet is sent. The master clock immediately records the master timestamp T2 when the message packet is received. , The master clock returns a message packet with the master clock timestamp T3 to the slave clock. After the slave clock receives the returned message packet, it immediately records the timestamp T4 of the slave clock.

Embracing the era of big data, interpreting 5G communication clock synchronization technology

At the same time, we assume that the two-way path is symmetrical, that is, the time from master to slave or slave to master is the same. Based on the above, we can easily get the transmission time of the two-way path.

Disadvantages: pure software calculation time, need to organize message transmission, need multiple calibrations, message transmission may have asymmetry, delay, etc., so the accuracy is not high.

Precision time protocol (PTP) theory

The IEEE 1588 PTP protocol is optimized on the basis of the NTP protocol. In terms of hardware, each network node must have a network interface card containing a real-time clock to meet the time stamp requirements.

IEEE 1588 network clock is mainly divided into ordinary clock OC (Ordinary clock) and boundary clock BC (Boundary clock). The clock with only one PTP communication port is the ordinary clock, and the clock with multiple PTP communication ports is the boundary clock. Each PTP port is independent Communication. In theory, we first determine an optimal clock as the master clock of the network. PTP uses the time stamp unit (TSU) to mark the master and slave clock timestamps. The TSU monitors the input and output data streams at the same time. When the preamble of the IEEE 1588 PTP data packet is recognized, a timestamp is issued to accurately mark the PTP time data packet. Arrival or departure time.

Embracing the era of big data, interpreting 5G communication clock synchronization technology

PTP protocol is based on pure software synchronization data packet transmission. PTP communication messages are mainly divided into: synchronization message Sync, follow message Follow_up (Note: Follow_up message is not required, some modes are not required, such as one-step mode), delayed request Message Delay_Req, delay response message Delay_Resp and management message.

Embracing the era of big data, interpreting 5G communication clock synchronization technology

IEEE 1588 PTP protocol time deviation correction:

• The master clock sends a Sync message to the slave clock and records the sending time tm1, and starts the timer at the same time. After the slave clock receives the message, it records the reception time ts1;

• The master clock then sends a Follow_up message carrying tm1;

• Calculate the offset time Offset based on the above two pieces of information;

• Interval time The master clock sends the second Sync message to the slave clock and records the sending time tm2. After the slave clock receives the message, it records the reception time ts2;

• The master clock then sends a Follow_up message carrying tm2;

• Correct the ts time through the above offset time Offset.

Based on the above steps, the modified ts time is consistent with the tm time.

Embracing the era of big data, interpreting 5G communication clock synchronization technology

IEEE 1588 PTP protocol delay calculation:

• The master clock sends a Sync message to the slave clock and records the transmission time t1. After the slave clock receives the message, it records the reception time t2;

• The master clock then sends a Follow_up message carrying t1;

• The slave clock sends a Delay_req message to the master clock to initiate the calculation of the reverse transmission delay and records the sending time t3. After the master clock receives the message, it records the reception time t4;

• After receiving the Delay_req message, the master clock replies with a Delay_resp message carrying t4.

Based on the above 4 timestamps, each time delay can be calculated.

Embracing the era of big data, interpreting 5G communication clock synchronization technology

SyncE+PTP theory

The most basic application premise of IEEE 1588 PTP synchronization is that it must be based on strictly consistent uplink and downlink clock frequencies. If the uplink and downlink clocks are not constant, the accuracy of time synchronization will be greatly reduced.

Embracing the era of big data, interpreting 5G communication clock synchronization technology

Using SyncE, the slave device obtains the master clock frequency through Ethernet, recovers the accurate clock frequency, and assists PTP to achieve phase alignment and time synchronization.

Embracing the era of big data, interpreting 5G communication clock synchronization technology

Microchip solutions

According to Wolfe Yu, engineer of Excelpoint Shijian: Microchip’s agent of Shijian has nearly 60-year-old complete clock solution providers such as Zarlink, Maxim Timing & Sync BU, Micrel, Vectron, Vitesse, Actel, etc., which can provide users with turnkey solutions. .

Embracing the era of big data, interpreting 5G communication clock synchronization technology

SyncE & IEEE 1588

Microchip’s multiple time solutions, products covering GPS, SyncE and IEEE1588 hybrid centralized systems and precise time systems, can meet the needs of different combinations of high, medium and low-end products.

Embracing the era of big data, interpreting 5G communication clock synchronization technology

Main features of ZL30735

• Up to 5 independent channel DPLLs;
• 3-channel NCO, separate XO, alternate clock mode mixed channel DPLL;
• Multi-channel Frac_N output frequency divider;
• Each channel supports any frequency conversion;
• Up to 10 channels of differential or single-ended input, 10 channels of differential or 20 channels of CMOS output;
• Meet ITU-T G.8262, G.8262.1, G.813, G.812, Telcordia GR-1244, GR-253;
• Meet ITU-T G.8261, G.8263, G.8273.2 (class A,B,C,D), G.8273.4;
• Embedded PPS;
• The jitter performance is less than 150 fs rms.

Embracing the era of big data, interpreting 5G communication clock synchronization technology

OCXO

Oven controlled crystal oscillator is abbreviated as OCXO (Oven Controlled Crystal Oscillator), which uses a constant temperature bath to keep the temperature of the quartz crystal resonator in the crystal oscillator constant. OCXO is composed of a thermostatic bath control circuit and an oscillator circuit. Usually, people use a differential series amplifier composed of a thermistor “bridge” to achieve temperature control.

Embracing the era of big data, interpreting 5G communication clock synchronization technology

Microchip has launched a variety of OCXOs for customers to choose from. The output frequency can reach up to 3GHz, the temperature stability can reach 0.15ppb, and the aging rate can reach 20ppb.

Embracing the era of big data, interpreting 5G communication clock synchronization technology

VCXO

Voltage-controlled oscillator refers to an oscillator circuit (VCO) whose output frequency corresponds to the input control voltage. The frequency is an oscillator VCO whose frequency is a function of the input signal voltage. The operating state of the oscillator or the component parameters of the oscillation circuit are controlled by the input control voltage. , It can form a voltage-controlled oscillator.

Embracing the era of big data, interpreting 5G communication clock synchronization technology

Microchip VCXO selection list:

Embracing the era of big data, interpreting 5G communication clock synchronization technology

In addition, Excelpoint Shijian can provide a complete turnkey solution based on Microchip’s integrated IEEE1588, SyncE PHY chip and IP protocol package to help 5G small base stations DU, RU and HUB and shorten the customer development cycle.

Embracing the era of big data, interpreting 5G communication clock synchronization technology

The Links:   6MBI20F-060 IS62WV12816BLL-55TLI

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