Embedded FPGA is not a dream, it can be done in one simple step

Embedded FPGA will no longer be a dream. According to Achronix, in the future, chip designers can simply add wire-to-wire interconnects to their SoC designs.

Embedded FPGAs will no longer be a dream. According to Achronix, in the future, chip designers can simply add wire-to-wire interconnects to their SoC designs.

Steve Mensor, vice president of marketing at Achronix semiconductor, said that this embedded FPGA (eFPGA) IP product called Speedcore is now ready and shipping. Although it did not disclose the number of shipments and the name of the customer, the company said that this product is now available to customers.

Speedcore symbolizes the company’s first foray into the IP business. Achronix has been producing its flagship FPGA product-Speedster 22i since 2013. Therefore, this is a long road for Achronix, because the company first announced its plans to develop eFPGA IP four years ago.

Nevertheless, Achronix sees a glimmer of light here, and is expected to make a profit for the first time this year, with a revenue of 12 million U.S. dollars. According to Mensor, the company expects its sales to grow by more than US$40 million in 2017, further making the eFPGA IP business an “important driving force” for Achronix’s growth.

Design Tools

Speedcore uses the same high-performance architecture as Achronix Speedster 22i FPGA. Speedcore eFPGA IP designed for computing and network acceleration applications will be integrated into other companies’ ASICs and used in data centers, wireless infrastructure and network equipment.

Mensor believes that the biggest advantage of eFPGA lies in its design tools. Over the years, Achronix has understood that customers need better design tools that bring them high-quality results, ease of use, and third-party integration, and these features are part of the “Achronix CAD Environment” (ACE) can provide share.

In order to be a part of the system, the eFPGA IP must have a functional design that is easy to integrate into the SoC. Achronix provides a GDS II version of Speedcore IP that allows customers to directly integrate into its SoC, and a customized version of ACE tools that allows customers to design, verify and program Speedcore eFPGA functions.

CPU casting?

The entire electronics industry knows that FPGAs are extremely popular. Just look at Microsoft’s Project Catapult.

Microsoft explained that this plan was created specifically to “accelerate Microsoft’s supercomputing foundation in network, security, cloud services, and artificial intelligence (AI),” and serves as its “post-CPU” (post-CPU) foundation. Various technologies-including GPU, FPGA and ASIC’s biggest attention.

The key to Microsoft’s Project Catapult lies in Altera Stratix V D5 FPGA. Mensor emphasized that the prevailing perception throughout the electronics industry is that Microsoft’s plan led to Intel’s decision to acquire Altera.

With AlphaGo, Googler’s custom Tensor processor unit has also inspired many engineers, prompting them to start thinking about everything from ASICs to GPUs and DSPs. Mensor explained that they are looking for technologies that can handle “accelerated unstructured search, machine learning, and artificial intelligence” more efficiently.

Achronix saw an opportunity in it.

Embedded FPGA is not a dream, it can be done in one simple step

FPGA application field and growth stage

FPGA has been popular in the market as a “glue chip” since the mid-1990s, and is now redefining its value as a co-processor of the CPU. In this role, FPGA can accelerate encryption/decryption, compression/decompression, or even preprocessing of data packets so that only relevant shared data can be transmitted and processed.

When performing unstructured searches, the parallel environment of FPGAs has proven to be very effective. For example, compared to CPUs designed to divide functions into smaller parts and work in sequence, FPGAs can complete the entire task in a single frequency cycle in a parallel manner.

When the wireless infrastructure must cover multiple geographic areas, FPGA is a backup trump card for programmable digital front-end and geographic area customization.

Wiring between chips

Although embedding FPGA in SoC can always bring good design ideas to designers, it is not easy for FPGA vendors to realize this wish.

“Wiring between different chips is very difficult,” Mensor said. The key to successfully integrating eFPGA IP is to minimize latency and increase throughput. The company emphasized that Achronix was the first to provide high-density FPGAs with embedded system-level IP.

For companies that “want to combine all the efficiency of ASIC design and the flexibility of eFPGA programmable hardware accelerators in the same chip”, Achronix provides the same eFPGA technology.

For IP vendors, the challenge of integration is that customers always have different ideas and methods for optimizing chip size, power consumption, and resource allocation required by specific applications. They also defined the number of lookup tables, the number of embedded memory modules, and the number of DSP modules.

But the problem is not necessarily the different ways customers build, but they often use different methods for chip testing and verification. Mensor explained that customers do not know how the IP vendor’s tools work with them. For example, “We often hear customers ask:’How can I use your IP to turn off the timing function?’”

Although Achronix does not integrate its IP for customers, its business depends on whether the tools provided are sufficient for customers to complete the design quickly

Embedded FPGA is not a dream, it can be done in one simple step

Achronix NT31P1 Achronix also acquired some third-party IP, including interface protocol, programmable IO, SerDes and PLL. So does Achronix encounter difficulties when developing FPGAs and meeting customer needs? Mensor said: “We always try to turn every problem we encounter into an opportunity.”

For Achronix, the key is to integrate the company’s FPGA architecture. The end result is a more streamlined Speedster 22i, its programmable IO, SerDes and interface controller take up less space, in contrast, competitors’ high-end FPGAs usually use about 50% of the chip area.

Embedded FPGA is not a dream, it can be done in one simple step

Achronix NT31P2 FPGA chip size comparison

Increase latency and transfer rate

Achronix believes that Speedcore eFPGA, which can realize wire-to-wire connection with SoC, helps eliminate a large number of programmable IO buffers, thereby reducing power consumption by half. In addition, Speedcore’s chip size is also smaller than that of standard FPGAs, which reduces the cost of eFPGA by more than 90%.

However, Mensor emphasized, “For most customers, the biggest determinant is latency and throughput.” According to Achronix, eFPGA has higher interface performance than a standalone FPGA, which is expected to be increased by 10 times. Throughput and latency performance.

Speedcore can now use TSMC’s 16FF+ process and develop with TSMC’s 7nm technology. The company also promised that through Speedcore’s modular architecture, Achronix can easily transfer the technology to different process technologies and stacks.

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