Design of RS-485 Balanced Differential Transmission System Based on DSP and FPGA

In the high-speed maglev transportation system, the vehicle-mounted speed measurement and positioning unit measures the position and speed of the vehicle in real time, and transmits the position and speed signals to the traction control system and operation control system on the ground through the radio system for the long-stator linear synchronization Feedback control of motor traction, command and safety protection of vehicle operation. The speed measurement positioning unit is the core and key of the closed-loop control of the traction and operation control system.

Author: Wang Han, Guo Xiaozhou

In the high-speed maglev transportation system, the vehicle-mounted speed measurement and positioning unit measures the position and speed of the vehicle in real time, and transmits the position and speed signals to the traction control system and operation control system on the ground through the radio system for the long-stator linear synchronization Feedback control of motor traction, command and safety protection of vehicle operation. The speed measurement positioning unit is the core and key of the closed-loop control of the traction and operation control system.

The speed measurement positioning unit is close to the suspension electromagnet, the long stator winding and the iron core, and is in the suspension magnetic field and the traction magnetic field. The electromagnetic environment is very complicated, which puts forward high requirements for the electromagnetic compatibility of its communication equipment. In addition, in order to meet the requirements of the traction control system, the accuracy requirements of the speed measurement and positioning signal are quite high. Therefore, the speed, real-time and reliability of the speed measurement and positioning signal transmission are all facing challenges. Based on the above considerations, this article puts forward the research on the synchronous 485 communication mode of maglev train based on DSP and FPGA to solve the above-mentioned challenges.

The realization method of synchronous 485

Taking into account the working environment and communication function requirements of the speed measurement positioning unit, when selecting the communication method between the unit and the car radio system, after analysis, this study adopts a synchronous communication method with a higher transmission rate, and uses a better shielding performance The twisted pair cable realizes RS-485 balanced differential transmission.

Interface design and communication protocol

The communication interface relationship between the speed measurement positioning unit and the vehicle-mounted radio control unit is shown in Figure 1. The vehicle-mounted radio control unit is the main controller, and the vehicle speed measurement and positioning unit is the controlled party. Both sides of the communication are composed of transceivers and controllers. RS-485 synchronous serial interface mode is adopted between the transceivers, and each interface has 4 pairs of differential lines.

In Figure 1, CLK is the clock signal, ANF is the radio request signal, UEF is the gate control signal, and DATA is the data signal. The vehicle speed measurement and positioning unit sends data to the radio control unit every 20ms, and the transmission rate is 512kbps. In order to prevent the interference of small pulse signals, the width of the ANF signal is 10 CLK signals; after the ANF signal becomes low, wait for the width of 10 CLK signals before the UEF starts to transition to valid. The ANF, UEF, and DAFA signals all change on the rising edge of CLK. When there is no signal transmission, UEF, DATA, ANF are all low level, and the clock signal keeps transmitting. The data transmission adopts the left shift mode, that is, the high bit is transmitted first, and then the low bit is transmitted. The format of the information frame is shown in Table 1.

Design of RS-485 Balanced Differential Transmission System Based on DSP and FPGA

Synchronous 485 transceiver implementation

In the communication system discussed in this article, both the vehicle speed measurement and positioning unit and the on-board radio control unit both use XC2S100 as the communication transceiver to simulate the timing of sending and receiving synchronous 485. The FPGA design of Sync 485 is mainly based on the Verilog hardware description language. The EDA tools used include ISE (including its internal integration tools) and Modelsim.

Clock and timing signal generation

The car radio control unit needs to generate a clock signal with a rate of 512k and an ANF signal every 20ms. In addition, when the unit receives positioning data serially, the receiving clock should be 16 times the 512k (baud rate clock), which is 8M. Therefore, the frequency divider is effectively used in the synchronous 485 communication mode.

For even-number division, you only need to design a counter to count. When the count reaches one-half of the division number, the clock level after division can be flipped; odd-number division is more complicated because the counter cannot count non-integer numbers. For counting, a certain algorithm is needed for processing. Here, the waveform after the function simulation of the odd frequency division module is shown in Figure 2.

The ANF signal is sent every 20ms, and the pulse width is 10 clock cycles each time. The generation of the ANF signal can be divided into two parts: first, a pulse signal with an interval of 20ms is generated, and then the width of the pulse signal is changed to 10 clock cycles.

Serial data transmission and reception

When generating serial data, according to the requirements of the communication protocol, the speed measurement positioning unit should serially shift out 72bits of data every 20ms. If one bit is shifted out in each transmit clock cycle, 72 clock cycles are required to move out all, so the gate control signal also needs to maintain the width of 72 clock cycles.

When receiving serial data, synchronous serial reception of a frame (72 bits) of data is different from asynchronous serial reception. Since the transceiver clock is not asynchronous, the first low level that appears after the idle state cannot be judged as the start of a frame, but the rising edge of the gate control signal (UEF) is used as the judgment of the arrival of a frame of data. In order to avoid the effect of glitches during data transmission, we still receive at 16 times the baud rate clock, that is, sampling once every 16 baud rate clock cycles. Therefore, each data will be in each bit of the transmission. The point is sampled.

The simulation timing diagram of serial data sending and receiving is shown in Figure 3.

Design of RS-485 Balanced Differential Transmission System Based on DSP and FPGA

Data exchange between transceiver and controller

Synchronous communication timing based on RS-485 is simulated using FPGA as a communication transceiver, but the communication data is ultimately exchanged with the CPU of the system. In the design of this communication method, both communication parties use TMS320F2812 as the communication controller. The data exchange between FPGA and DSP must meet a certain time sequence to ensure that the speed measurement positioning unit transmits position and speed signals to the vehicle radio control unit in real time. In this system, the DSP controller adopts C language for software design.

Data exchange between DSP and FPGA on the side of speed measurement positioning unit

The external address space available for the external memory XINTF of TMS320F2812 is XINTF0, XINTF2 and XINTF6. Among them, XINTF0 uses XZCS0AND1 as the chip selection signal, and the external memory expansion space is 8K; XINTF2 and XINTF6 use XZCS2 and XZCS6AND7 respectively as the chip selection signal, and the external memory expansion space is 0.5M. When the speed measurement positioning unit sends position and speed information, it is transmitted to the FPGA through the DSP data line. The DSP finds the corresponding address according to the corresponding external memory chip selection signal, and writes the address after obtaining a new positioning data from the bottom sensor. The corresponding hardware connection block diagram is shown in Figure 4.

According to the requirements of the agreement, each time the positioning information is sent, it includes 5 bytes of user data and 2 bytes of CRC. Therefore, the 16bits data line needs to be sent at least four times in a row to completely transmit the underlying positioning information to FPGA.

In order to reduce hard wiring, only the upper five bits of the address line are connected here, and the lower four bits of the address line are decoded from 4 to 16, and the highest address line is used as the enable signal of the decoder. Take the four addresses corresponding to an external memory chip select signal. For example, if the chip select signal XZCS2 is low, the four addresses 0xe0000, 0xe4000, 0xe8000, and 0xec000 can be selected as the address for the DSP to write data to the FPGA.

Since each different address corresponds to an address decoding value, it can be considered that a positioning information transmission is completed only after the four decoding values ​​appear. At this time, the continuously received seven bytes are added to the frame header and frame end as a frame of data sent by the speed measurement positioning unit to the on-board radio control unit.

Data exchange between DSP and FPGA on the side of the car radio control unit

In order to avoid occupying too much CPU resources, the DSP in the car radio control unit does not use the query mode when reading data from the FPGA, but uses an external interrupt to receive the data. Connect the 16bits data line of the DSP to the FPGA, and also connect the XINT1 of the DSP to the I/O pin of the FPGA. If XZCS0AND1 is selected as the external memory chip select signal, the addressing space range for DSP to read data from FPGA is 0x002000-0x004000, and the data read in this address range is the positioning data transmitted to the DSP on the data line. The corresponding hardware connection block diagram is shown in Figure 5.

Design of RS-485 Balanced Differential Transmission System Based on DSP and FPGA

Since one frame of data transmitted from FPGA to DSP is 72 bits, it takes 5 times to transmit through the 16 bits data line, and an external interrupt is generated every 16 bits data arrives. Suppose the baud rate clock is 512k. Assuming that the complete frame of data from the positioning unit is 0x02123456789abcde03, the data that the car radio unit forwards to the DSP through the 16bits data line is 0x0002, 0x1234, 0x5678, 0x9abc, and 0xde03. The timing of data and interrupt signal generation is shown in Figure 6. It can be seen from Figure 6 that every time dataout is correspondingly removed, an external interrupt signal xint1 will be sent accordingly. Once the DSP receives an external interrupt, it reads the signal value from the 16bits data line in the interrupt service subroutine. In order to receive a frame of signal completely, a 16-level FIFO can be defined in the external interrupt service program. When the data read from the bottom layer of the FIFO is 0x02, the start of a frame of data can be judged (if in the user data and calibration If there is 0x02 in the verification value, the corresponding character must be escaped), and then receive the following data in turn to get a complete frame of positioning information.

Schematic diagram of both parties in communication

According to the above description of the synchronization 485 implementation method, the top-level schematics drawn by the ECS tool in ISE are shown in Figure 7 and Figure 8. It includes two parts: synchronous data sending of speed measurement and positioning unit and synchronous data receiving of vehicle radio control unit.

In Figure 7, addr_decode is the address decoding module, which is used to completely receive a frame of positioning information from the DSP; tra485data is the serial data and gate control signal sending module. Among them, din (15:0) directly comes from the 16bits data line of the DSP; addr (3:0) is connected with the A17~A14 address line of the DSP; clkin and anfin signals are provided by the car radio control unit. The output dataout and uefout are sent to the car radio control unit after output buffering and differential level conversion.

In the schematic diagram of the vehicle radio control unit synchronization data receiver shown in Figure 8, divide_512k is the sending clock generation module to generate the baud rate clock required for communication; anf_shift is used to generate the radio request signal; rec485data is used for serial reception The positioning information is forwarded to the communication controller through the dataconvert module. Among them, Dataout (15:0) is directly connected to the DSP through the data line, and Xint1 is connected to the external interrupt 1 of the DSP. Anfout and clkout are obtained by dividing the input crystal frequency, and then sent to the vehicle speed measurement and positioning unit after output buffering and differential level conversion.

Design of RS-485 Balanced Differential Transmission System Based on DSP and FPGA

Concluding remarks

In the special communication environment of the high-speed maglev train, the synchronous communication method based on the RS-485 physical layer embodies the advantages of strong anti-interference, good real-time performance, and low bit error rate, and the realization principle is simple. The communication transceiver implemented by FPGA is designed to be flexible and highly reliable, and its function has been verified in practical applications.

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