Comparison of various FPGA prototype verification platform technologies, the application of verification tools is not limited to chips

Electronic Design Automation-Electronic Design Automation, EDA for short. As the most upstream chip design, the job of EDA software is to carry out layout, layout, design rule checking, etc. in a space as small as a chip, just like carving out an aircraft carrier model on a grain of rice.

Electronic Design Automation-Electronic Design Automation, EDA for short. As the most upstream chip design, the job of EDA software is to carry out layout, layout, design rule checking, etc. in a space as small as a chip, just like carving out an aircraft carrier model on a grain of rice.

Before EDA came out, designers had to manually complete basic work such as circuit design and wiring. With the improvement of chip integration and the diversification of performance, chip design requirements have become more and more complicated. Tens of billions of transistors need to be integrated on a fingernail-sized chip. Such a subtle and grand project is no longer a simple manpower. Within the scope of coverage, the importance of EDA is self-evident.

According to different application scenarios, the use of EDA tools is mainly divided into three categories: design, verification and manufacturing. The increase in complexity of large-scale integrated circuit design makes chip verification face huge challenges in terms of capital and time. Early developers want to verify whether the chip design meets the presets. They only have to wait for extremely long simulation results or wait for the tape-out results. Once the results are not as expected, whether it is a re-simulation or a second tape-out, the result will be extremely high. the cost of. Therefore, when Xilinx launched the Field Programmable Logic Gate Array (FPGA), developers could use the FPGA board to piece together an effective process to verify the design, and the FPGA prototype verification solution came into being. Tape-out is cheaper and faster than simulation, which has become the best choice for developers to verify the effectiveness of their designs.

01 FPGA-based physical prototype verification

Just like architects need to test various parameters such as earthquake resistance, wind resistance, structural strength, etc. through models before designing a building and starting construction, chip and system developers also need to “prototype verification” of the design before tape out-that is Whether the chip and system performance under imitating real software application conditions meets the requirements of actual application scenarios.

FPGA has a wide range of applications. It has made achievements in communication, computing, control and other fields, and because of its reconfigurable internal circuit characteristics, it can almost completely mirror the logic design of the chip, and it is also regarded as a cost-effective Chip verification infrastructure. FPGA prototype verification is the current mainstream and mature chip verification method for prototype verification-it verifies the functions of the ASIC by transplanting RTL to a field programmable gate array (FPGA), and can start after the basic function verification of the chip is passed Drive development, drive and application development can be carried out until the chip is Tape Out and returned to the chip. When the chip is returned to the chip, the application can be directly adapted based on the FPGA version of the driver, that is, it can be applied to the SoC chip, and the time control of the SoC chip Time-to-Market is perfect. In addition to software development in advance, FPGA prototype verification is a cost-effective verification method in terms of cost, and it can be said to be very close to the people in terms of price. The more important FPGA prototype is also faster in running speed: it is certainly several orders of magnitude faster than EDA verification in speed, and even compared with Emulator, its performance has a rolling advantage. Among these advantages, “soft and hardware collaborative development before tape-out” is the most irreplaceable part of FPGA physical prototype verification. Early software-driven development and application development based on this technology platform are useful for shortening the time-to-market cycle of the final chip. Significant.

Today, when software and hardware are deeply customized and require one-stop delivery from chip to application, the importance of the FPGA prototype platform is further enhanced. In 2000, Hardi Electronics, a company founded in Sweden, officially launched an FPGA-based prototype system HAPS. HAPS can quickly assemble ASIC prototype systems in a variety of ways, saving customers months of time in the critical verification phase. In 2007, Synplicity acquired Hardi for USD 24 million, and Synopsys acquired Synplicity for USD 227 million in 2008. HAPS developed to HAPS-80 in 2014 after several generations, and it is still the fastest prototype verification in the industry. Speed ​​up the platform.

02 Several challenges and solutions of physical prototype verification tools

1 Capacity limitations and performance requirements For large designs (more than 20 million equivalent ASIC gates), one FPGA often cannot accommodate. At this time, multiple FPGAs must be interconnected to verify the entire design. In this case, it is necessary to The design is partitioned. Partition introduces new problems, and these problems do not actually exist in the chip. Many times it takes a lot of manpower to implement a usable Partition solution, which is only a last resort method limited by the capacity of the FPGA.

The biggest problem introduced by Partition is the surge in demand for I/O. Although FPGA has more than 1000 available I/O, if a complete SoC is split into several parts of the same size, the difference between each part The number of interconnected signals often exceeds 1000, so when the number of I/Os is limited, TDM (Time Division Multiplex) must be used, that is, multiple parallel signals inside the FPGA are converted into high-speed serial signals and transmitted through FPGA I/O To another FPGA, and then demultiplex, convert into parallel signal, realize the signal transfer from one FPGA to another FPGA. The introduction of TDM solves the I/O bottleneck, but Mux and De-Mux introduce additional delays, causing the Path of Cross-FPGA to become a critical path, which further reduces the operating frequency of FPGA. It can be said that Partition is a last resort The final result is only a usable solution rather than an ideal solution.

On the other hand, due to the frequent increase and decrease of modules in SoC prototype verification, frequent changes to the Partition scheme are required. If it is handled manually, it will take a lot of effort to get a usable but compromised scheme mentioned above. In addition, processing a large number of Cross-FPGA signals is very error-prone, so for large-scale SoC FPGA prototype verification, automated tools must be used to complete Partition, which is also a new challenge for EDA tools.

Synopsys’ HAPS prototype verification solution has a unique automatic and intervening segmentation function. It also provides a system-level cross-FPGA timing analysis tool, provides timing models for HSTDM IP, cables and I/O, and can easily handle TDM paths The multiple constraints on the above provide optimized and reliable timing for the design of multiple FPGAs, ensuring the high-speed performance and stability of the platform.

2 Iteration speed

Due to the high frequency of SoC chip design, in order to make the prototype verification platform as close as possible to the performance of the SoC chip, developers expect to make the FPGA prototype platform run at the highest possible frequency. However, because the RTL code of the SoC is designed for chip implementation, The existence of a large amount of deep-level combinational logic (which can save chip area) makes it difficult for SoC RTL code to implement timing closure on FPGA, which can only reach a few MHz. For large-scale SoCs, the internal CPU/GPU/CODEC/NPU and other calculation and codec modules have complex logic, which often becomes the Timing Wall of the entire design, resulting in the timing optimization process taking up 30-40% of the FPGA Implementation process.

Based on Synopsys’ HAPS prototyping solution, while dividing and optimizing the design timing, it also fully considers the challenges of subsequent FPGA placement and routing. During synthesis, HAPS uses unique technology to enhance and optimize the synthesis results of a single FPGA. , Which can effectively reduce the time of later Vivado placement and routing, combined with technologies such as multi-core and multi-process synthesis, effectively reduce the time of each link and speed up the iteration.

3 interface scheme

The high-speed synchronous interface between the external daughter board and FPGA I/O has always been a pain point and difficulty of FPGA: On the one hand, compared with ASIC, FPGA has limited space for adjusting I/O timing, and it cannot be like ASIC. The Skew between FPGA I/O signals can be flexibly adjusted through timing constraints. As a result, the Path Skew between parallel signal interfaces is difficult to control within an ideal range, which will eventually lead to data sampling failures. Lowering the frequency is often a kind of Effective way, but the interface between some controllers and PHY needs to meet the standard specifications and cannot be reduced indefinitely. In this case, sometimes we can only try to fix the timing and even modify the code.

On the other hand, the number of daughter boards used for prototype verification is not large, and they are often not sold in the market. In many cases, they need to design by themselves, which further brings uncertainty to debugging and extends the debugging cycle. Debugging of high-speed interfaces often consumes a lot of human resources. In many cases, problems are solved by debugging experience and inspiration. This is not only time-consuming and laborious, but also ineffective.

Synopsys’ HAPS prototype verification solution provides users with a variety of flexible interface solutions, including a rich collection of external daughter cards, and speed reduction bridge solutions; and through the HAPS Connect Program with industry partners, it provides users with a wider range of Expansion space.

4 Observability FPGA is also a chip product, so the internal signals cannot be directly observed. Usually need to use FPGA Debug tool to select the signal to be observed before generating the Bit file. When the Bit file is loaded and running, the specified signal waveform must be observed through the supporting Debug tool. However, due to the capacity of the Block RAM and signal optimization, the efficiency of such debugging is relatively low.

Synopsys HAPS prototype verification platform provides a variety of flexible debugging methods. The DTD (Deep Tracking Debug) function provides users with multi-FPGA real-time speed RTL-level signal joint waveform debugging, which can observe waveforms of thousands of signals per second, and further combines with the key signal extraction function of Verdi/Siloti, which can significantly expand the signal The scope of observation. GSV is another debugging function that is widely used by users. It can provide a snapshot of all the internal registers of the design and effectively help the software and hardware teams analyze and locate system problems in a variety of actual debugging scenarios.

5 Product maturity

Prototype verification is a technology with high barriers. It connects chip design and final application in series. It needs strong applicability and flexibility to adapt to the rapid development and diversity of chip research and development. Through the cooperation with first-line chip developers, Using the ecosystem, continuous evolution and iterative technology can always help chip developers to achieve “Shift-Left” research and development, and speed up the time to market.

Since the launch of the first prototype verification product HAPS-10 in 2003, Synopsys has continued to launch 7th generation products, which have been tested by the market for a long time. In order to meet the evolving prototype verification requirements, it has added many unique product features, such as UMRBus , Hybrid prototype verification, UPF-based low-power system verification, HAPS GateWay, etc., are the best solutions to accelerate software development and chip design verification. More than 200 companies worldwide have deployed the latest generation of HAPS-80, including nine of the top ten semiconductor companies, with shipments exceeding 3,000 units this year.

At present, more than 50 chip design companies in China have deployed the HAPS platform, further verifying the market leading position of HAPS prototype verification.

Comparison of various FPGA prototype verification platform technologies

At present, the common FPGA prototyping platforms on the market can be divided into two categories, one is the FPGA board (Build Your Own, hereinafter referred to as BYO) made by the chip design company; the other is the commercial FPGA platform, such as Synopsys’ HAPS program.

Regarding some of the specific considerations mentioned above, the comparison of various prototype verification platforms is as follows:

Comparison of various FPGA prototype verification platform technologies, the application of verification tools is not limited to chips

Obviously, Synopsys’ HAPS solution has an absolute advantage in comprehensiveness, maturity, and support for large-scale design.

03 Physical prototype

The application of verification tools is more than just chips

Chip is a hardware industry as well as a software industry. It also involves downstream application scenarios and upstream high-precision design. In the era of intelligence empowered by technology, chips not only support all aspects of the digital economy, but also their role in empowering various industries cannot be underestimated. From 5G, self-driving cars, artificial intelligence, etc., chip applications are almost everywhere imaginable. Electronic products even include all aspects from aerospace to military technology. With the accelerated development of artificial intelligence and 5G, as well as the acceleration of the development of new infrastructure in the digital age, there will be more and more application scenarios for chips in the future, and the demand for customized chips will also increase. As the developers who hold the key to the future world, they must cooperate more closely with system manufacturers to research and develop, so that the innovation of chip technology can finally enable the application of technology.

Taking the artificial intelligence face recognition scene as an example, searching for lost children in a large number of people requires super fast response ability to seize the opportunity to recognize and find the target object in the first time. The software supports artificial intelligence algorithms and chips. The super computing power provided allows complex algorithms to realize inferences within milliseconds. Physical prototype verification allows software development and chip development to proceed simultaneously without waiting for each other. This technology will promote the ecological integration of chips and technology applications, allow technological progress to enter a rapid mode, and accelerate future imagination into reality.

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