Be careful when dealing with ADC output, “Grounding Technology Guide” is here

Although many converters have three-state outputs/inputs, these registers are still on the chip. They enable the data pin signal to be coupled to the sensitive area, so the isolation buffer is still a good design method. In some cases, it is even necessary to provide additional data buffers on the analog ground plane next to the converter output to provide better isolation.

Although many converters have three-state outputs/inputs, these registers are still on the chip. They enable the data pin signal to be coupled to the sensitive area, so the isolation buffer is still a good design method. In some cases, it is even necessary to provide additional data buffers on the analog ground plane next to the converter output to provide better isolation.

It is a good idea to place the data buffer next to the converter to isolate the digital output from the data bus noise (as shown in Figure 1). The data buffer also helps to minimize the load on the converter’s digital output, while providing a Faraday shield between the digital output and the data bus (as shown in Figure 2).

Be careful when dealing with ADC output, “Grounding Technology Guide” is here

Figure 1. Proper grounding of a mixed-signal IC with low internal digital current

Be careful when dealing with ADC output, “Grounding Technology Guide” is here

Figure 2. A high-speed ADC using a buffer/latch at the output has enhanced immunity to digital data bus noise

The series resistance between the ADC output and the buffer register input (labeled “R” in Figure 1) helps to minimize digital transient currents, which may affect converter performance. The resistor can isolate the digital output driver from the capacitance of the buffer register input. In addition, an RC network composed of series resistors and buffer register input capacitors is used as a low-pass filter to slow down fast edges.

A typical CMOS gate combined with PCB traces and vias will generate a load of about 10 pF. If there is no isolation resistor, a logic output slew rate of 1 V/ns will produce a dynamic current of 10 mA:

Be careful when dealing with ADC output, “Grounding Technology Guide” is here

When driving a register input capacitance of 10 pF, a 500 Ω series resistor minimizes the transient output current and produces a rise and fall time of approximately 11 ns:

Be careful when dealing with ADC output, “Grounding Technology Guide” is here

Since the TTL register has a higher input capacitance, which can significantly increase the dynamic switching current, it should be avoided.

Buffer registers and other digital circuits should be grounded and decoupled to the digital ground plane of the PC board. Note that any noise between the analog and digital ground planes can reduce the noise margin on the converter’s digital interface. Since digital noise immunity is in the hundreds or thousands of millivolts, it is generally unlikely to be a problem. The analog ground plane noise is usually not high, but if the noise on the digital ground plane (relative to the analog ground plane) exceeds hundreds of millivolts, measures should be taken to reduce the impedance of the digital ground plane to keep the digital noise margin acceptable s level. In any case, the voltage between the two ground planes must not exceed 300mV, otherwise the IC may be damaged.

It is better to provide independent power supplies for analog circuits and digital circuits. The analog power supply should be used to power the converter. If the converter has a designated digital power supply pin (VD), it should be powered by an independent analog power supply, or be filtered as shown in Figure 3. All converter power pins should be decoupled to the analog ground plane, and all logic circuit power pins should be decoupled to the digital ground plane, as shown in Figure 3. If the digital power supply is relatively quiet, you can use it to power analog circuits, but be careful.

Be careful when dealing with ADC output, “Grounding Technology Guide” is here

Figure 3. Grounding and decoupling points

In some cases, it is not possible to connect VD to an analog power supply. Some high-speed ICs may use a +5 V power supply to power their analog circuits, and use a +3.3 V or less power supply to power the digital interface in order to interface with external logic. In this case, the +3.3 V pin of the IC should be directly decoupled to the analog ground plane. It is also recommended to connect the ferrite bead in series with the power supply trace to connect the pin to the +3.3 V digital logic power supply. The sampling clock generation circuit should be treated the same as the analog circuit, grounded and deeply decoupled to the analog ground plane.

Grounding for high frequency operation

It is generally advocated that power and signal currents are best returned through the “ground layer”, and this layer can also provide reference nodes for converters, reference voltage sources and other sub-circuits. However, even the extensive use of ground planes does not guarantee that AC circuits have a high-quality ground reference.

The simple circuit shown in Figure 4 is made with a two-layer printed circuit board. On the top layer, there is an AC and DC current source, one end of which is connected to Via 1, and the other end is connected to Via 2 through a U-shaped copper trace. Both vias pass through the circuit board and are connected to the ground plane. Ideally, the impedance in the top connector and the ground loop between via 1 and via 2 is zero, and the voltage on the current source is zero.

Be careful when dealing with ADC output, “Grounding Technology Guide” is here

Figure 4. Schematic diagram and layout of the current source. U-shaped traces are laid out on the PCB and return through the ground plane

This simple schematic diagram is difficult to show the inherent subtleties, but understanding how the current flows from via 1 to via 2 in the ground plane will help us see the actual problem and find the elimination of high-frequency layout grounding Noise method.

Be careful when dealing with ADC output, “Grounding Technology Guide” is here

Figure 5. The flow of DC current on the PCB shown in Figure 4

The flow of DC current shown in Figure 5 selects the path with the smallest resistance from via 1 to via 2 in the ground plane. Although some current diffusion will occur, basically no current will deviate from this path substantially. On the contrary, AC current chooses the path with the least impedance, which depends on the inductance.

The inductance is proportional to the area of ​​the current loop. The relationship between the two can be explained by the right-hand rule and the magnetic field shown in Figure 6. Within the loop, the magnetic fields generated by the currents flowing along all parts of the loop reinforce each other. Outside the loop, the magnetic fields generated by different parts weaken each other. Therefore, the magnetic field is in principle restricted to the loop. The larger the loop, the greater the inductance, which means that for a given current level, it stores more magnetic energy (Li2) and has a higher impedance (XL = jωL), and therefore will produce a greater voltage at a given frequency.

Be careful when dealing with ADC output, “Grounding Technology Guide” is here

Figure 6. Magnetic field lines and inductive loops (right-hand rule)

Which path will the current take in the ground plane? Naturally, it is the path with the lowest impedance. Considering the loop formed by the U-shaped surface lead and the grounding layer, and ignoring the resistance, the high-frequency AC current will flow along the path with the lowest impedance, that is, the smallest enclosed area.

In the example shown in the figure, the loop with the smallest area is obviously the loop formed by the U-shaped top trace and the ground layer directly below it. Figure 5 shows the DC current path, and Figure 7 shows the path chosen by most AC currents in the ground plane. It has the smallest area and is located directly below the U-shaped top trace. In practical applications, the resistance of the ground plane will cause the low-IF current to flow somewhere between the direct return path and directly below the top wire. However, even if the frequency is as low as 1 MHz or 2 MHz, the return path is close to below the top trace.

Be careful when dealing with ADC output, “Grounding Technology Guide” is here

Figure 7. AC current path with no resistance (left picture) and resistance (right picture) in the ground plane

Sampling clock considerations

In a high-performance sampling data system, a low-phase noise crystal oscillator should be used to generate the ADC (or DAC) sampling clock, because the sampling clock jitter will modulate the analog input/output signal and increase the noise and distortion floor. The sampling clock generator should be isolated from the high-noise digital circuit, grounded and decoupled to the analog ground plane at the same time, just like the operational amplifier and ADC.

The influence of sampling clock jitter on ADC signal-to-noise ratio (SNR) can be approximated by the following formula:

Be careful when dealing with ADC output, “Grounding Technology Guide” is here

Among them, f is the analog input frequency and SNR is the SNR of the perfect infinite resolution ADC. At this time, the only noise source comes from the rms sampling clock jitter tj. A simple example shows that if tj = 50 ps (rms) and f = 100 kHz, then SNR = 90 dB, which is equivalent to a dynamic range of about 15 bits.

It should be noted that tj in the above example is actually the root-sum-square (rss) value of the external clock jitter and the internal ADC clock jitter (called aperture jitter). However, in most high-performance ADCs, the internal aperture jitter is negligible compared to the jitter on the sampling clock.

Since the decrease in signal-to-noise ratio (SNR) is mainly caused by external clock jitter, measures must be taken to make the sampling clock as noise-free as possible and only have the lowest possible phase jitter. This requires the use of a crystal oscillator. Many manufacturers offer small crystal oscillators that can produce low jitter (less than 5 ps rms) CMOS compatible output.

Ideally, the sampling clock crystal oscillator should refer to the analog ground plane in the separated grounding system. However, system limitations may make this impossible. In many cases, the sampling clock must be derived from a higher frequency, multi-purpose system clock generated on the digital ground plane, and then must be passed from the origin on the digital ground plane to the ADC on the analog ground plane. The ground noise between the two layers is directly added to the clock signal and generates excessive jitter. Jitter can cause a decrease in the signal-to-noise ratio, and it can also produce interference harmonics.

This problem can be solved to a certain extent by using a small radio frequency transformer (as shown in Figure 8) or a high-speed differential driver and receiver, and transmitting the sampling clock signal as a differential signal. If you use the latter, you should choose ECL to minimize phase jitter. In a single +5 V power supply system, the ECL logic can be connected between ground and +5 V (PECL), and the output is AC coupled to the ADC sampling clock input. In either case, the original main system clock must be generated from a low phase noise crystal oscillator.

Be careful when dealing with ADC output, “Grounding Technology Guide” is here

Figure 8. Sampling clock distribution from the digital-to-analog ground plane

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