“The traditional telecommunications network is a synchronous network, and the telecommunications offices and each office must maintain a synchronized state. Therefore, there must be a synchronization distribution system to ensure that the signals transmitted through the line can still maintain the original synchronization relationship. In a PDH network, the clock signal is recovered from the T1 or E1 line. Synchronous Supply Unit (SSU) or Building Integrated Timing Supply (BITS) is a commonly used method in network synchronization, which is mainly based on the master clock as the synchronization network The next-level device in the device provides the clock.
Author: Yang Yongtao
The traditional telecommunications network is a synchronous network, and the telecommunications offices and each office must maintain a synchronized state. Therefore, there must be a synchronization distribution system to ensure that the signals transmitted through the line can still maintain the original synchronization relationship. In a PDH network, the clock signal is recovered from the T1 or E1 line. Synchronous Supply Unit (SSU) or Building Integrated Timing Supply (BITS) is a commonly used method in network synchronization, which is mainly based on the master clock as the synchronization network The next-level device in the device provides the clock. BITS is mainly used in North America, and SSU is mainly used in other places. This article uses Dallas semiconductor’s DS26502 to provide a complete front-end solution for BITS/SSU applications or systems that use T1/E1 to transmit timing information.
Basic concepts of network synchronization
At present, most telecommunications networks are synchronous networks. Whether it is 2G GSM, 3G CDMA or the current popular WiMAX network, their operation and development must first solve the synchronization problem. Synchronization means that the frequency or phase between signals maintains a certain specific relationship, that is, they appear at the same rate within the corresponding effective time. Synchronizing all clocks of a telecommunications network is to ensure that the sending and receiving nodes sample data at the same rate to prevent data transmission loss. A public switched telephone network (PSTN) needs to realize bit synchronization, frame synchronization and network synchronization at the same time to be able to work normally.
The synchronization of the network is based on the clock layered structure, as shown in Figure 1. The top layer is the primary reference clock (PRC) or primary reference source (PRS), with the highest clock accuracy, which can reach 10-11. PRC/PRS can be generated by a cesium atomic clock, or received by GPS or GLONASS. The next layer is the Synchronous Supply Unit (SSU) or Building Integrated Timing Supply (BITS). SSU/BITS has retention performance. When it loses synchronization with PRC/PRS, it can generate a clock with a precision higher than its inherent free-running precision in a short period of time. SSU/BITS is usually implemented by a digital phase-locked loop (DPLL) driven by a rubidium clock, and can be an independent product that only has a clock function without data transmission. The third layer is SDH equipment clock (SEC) or SONET minimum clock (SMC). SEC/SMC also has retention performance, but its retention and free oscillation accuracy performance are lower than the requirements for SSU/BITS. SEC/SMC is usually implemented by DPLL driven by Oven Controlled Crystal Oscillator (OCXO) or Temperature Controlled Crystal Oscillator (TCXO), which can be part of a network product or a single board. The second layer and the following layers in the hierarchical structure can have the same clock accuracy as the PRC/PRS as long as the path to the PRC/PRS is not interrupted.
Figure 1 Network synchronization clock hierarchical structure
There are currently two major standards organizations responsible for formulating network clock requirements. The GR-XXX-CORE issued by Telcordia is mainly for North America, while the ITU is targeting other regions of the world through the ITU-T G.XXX series of documents. The digital synchronization that China has built is based on the PDH environment, that is, the PDH circuit is used to transmit timing signals. With the development of the transmission network from PDH to SDH, the transmission institute formulated the “SDH Network Transmission Synchronization Network Timing Method”. China adopts two kinds of signals, 2048kb/s and 2048kHz, as the standard interface signal of the synchronization network. The 2048kHz signal complies with the G.703 recommendation, while the 2048kb/s complies with both the G.703 and G.704 recommendations.
Basic functions of DS26502
In the early days when PDH was used to transmit synchronous clocks, since there was no dedicated clock recovery device, the usual approach was to use a single-chip T1/E1 transceiver with an integrated framer (FRAMER), such as the line recovery clock RCLK of DS2155, for synchronization. ’S reception. This solution can be used to complete the synchronization clock transmission, but it also has some shortcomings, because the monolithic transceiver is not a dedicated clock recovery chip, so there will be a lot of idle pins first, resulting in waste of resources, complex design, and some irrelevant processing Cause unnecessary power consumption. In addition, because there is no special processing in the clock configuration, some special requirements of ANSI/ITU-T regarding synchronous clock signals cannot be realized.
DS26502 is a dedicated clock recovery device for SSU/BITS introduced by Dallas Semiconductor. The system structure is shown in Figure 2. Its receiving end can recover the clock from T1, E1, 64kHz composite clock (64KCC) and 6312kHz synchronization timing interface. In T1 and E1 modes, it can also restore the synchronization status message (SSM). The sending part can be directly connected to the T1, E1 or 64KCC composite clock synchronization interface, and can also provide SSM in T1 and E1 modes. Within the input and output synchronization clock frequencies supported by DS26502, it can achieve any frequency conversion. In addition, DS26502 also has a separate output to provide a 6312kHz clock signal.
Figure 2 System structure of DS26502
In terms of physical characteristics, DS26502 can be set by software, supporting both long-distance and short-distance at the same time. It can match different line interfaces such as 75/100/110/120 without changing the hardware. In the redundant design, in order to facilitate protection switching, The output of the transmitting end can be quickly turned off through the device pins; the jitter attenuator inside the chip can be placed on the transmitting side or the receiving side, and has a bypass mode; when the line has LOS, AIS, and LOF status , There are hardware pin output instructions, you can easily find problems by connecting LED lights; there are various control methods, which can be read and written through parallel, serial or hardware controller ports. When using 8-bit parallel control ports, you can choose Intel or Motorola. A kind of bus mode, the general SPI interface is used in the serial mode. In terms of protocol, DS26502 complies with all the specifications of ANSI on T1 and ITU-T on E1, complies with G.703 2048kHz synchronization interface and 64kHz centralization (option A) and co-directional timing interface, complies with G.703 Appendix II 64kHz and 6312kHz Japan synchronization interface.
Application of DS26502
DS26502 has two main operating modes: software mode and hardware mode. The main difference between them is the control mode of the device. In software mode, the microcontroller uses a serial or parallel bus to connect to the internal control register of the DS26502 in Figure 2. This external controller initializes the DS26502, reads and writes data, and other operations; in the hardware mode, the original serial or Parallel communication interface pins have been given functions again, through the new logic definition of these pins, you can directly control the internal work of the DS26502 without a peripheral processor. This is one of the advantages of the hardware model. In the actual design, whether to use the hardware mode depends on the special requirements of the specific application. The design needs to focus on whether the target application will use some functions that can only be used in software mode. This is also a limitation of using hardware mode. Some functions cannot be used in this mode, or some functions cannot be performed like software mode. Settings, such as software reset, interrupt masking, and status register read and write cannot be performed.
In order to fully utilize the characteristic of DS26502, adopt the software way to carry on the design in the design, as shown in Fig. 3. The high-speed eight-bit single-chip microcomputer DS80C320 is selected as the main controller, and the entire board uses MAX809 for reset control.
Figure 3 Application block diagram of DS26502
The line-side design of DS26502 is exactly the same as the standard T1/E1 circuit design. Figure 4 shows the interface circuit. Its LIU interface can be switched by software between T1/E1/64KCC/6312kHz networks without changing the external design. The 64kcc here refers to the G.703-compliant 64kHz synchronization interface. At this time, the 64kHz clock signal contains two frequencies of 8kHz and 400Hz through the encoding. The sending and receiving of the LIU are completely independent, which means that the sending end can be connected to the T1 (E1) circuit, while the receiving end adopts the E1 (T1) mode. It should be noted that there is no clear regulation on how to perform 6312kHz pulse shaping in the G.703 specification, so 6312kHz is slightly different from other modes. When receiving, 6312kHz is the same as other modes. It is received through RTIP and RRING, but when sending, it is only a 0～3.3V signal output by the TCLKO pin, and it is not sent to the line through TTIP and TRING for output. It needs to be filtered by an external source. To achieve 6312kHz sine waveform.
Figure 4 The interface circuit of DS26502
When the line interface needs to be connected to a monitoring port, due to the relationship between the termination resistance of the E1/T1 line and the isolation resistance of the monitoring port, there is resistive attenuation in the line at this time, so the E1/T1 receiving line needs to be able to provide different Receive gain. For this kind of application, DS26502 can provide a monitoring application mode on the receiving side. By setting the two registers of MM0 and MM1, DS26502 can provide a receiving gain of up to 32dB to compensate for the problem of signal amplitude reduction after voltage division. It should be noted that this purely resistive loss and gain are different from the cable loss characteristics on E1/T1 transmission lines.
The output of DS26502 is the 2M synchronous clock that needs to be extracted from the line. This clock is sent all the way to the FPGA for processing, which can improve flexibility and facilitate the change of the pin configuration of the single board, and the other is sent to the clock driver for other devices on the board to use. In addition to extracting the clock from the line, DS26502 can also receive the 2.048MHz synchronous square wave clock specified in Part 10 of ITU G.703.
The synchronization status message SSM (Synchronization Status Message) is used to transmit the quality level of the timing signal in the synchronization timing link, so that the node clock in the SDH network and the synchronization network can obtain the information of the upstream clock through the interpretation of the SSM, and perform the control on the clock of the node. Corresponding operations (such as tracking, switching, or transfer to hold), and pass the node synchronization information to the downstream. It uses 4bit encoding, a total of 16 kinds of signals, reflecting different quality levels. Due to the long transmission distance of the 2Mb/s signal and the synchronization status information (SSM) function, the 2Mb/s signal is preferentially used in the synchronization network. DS26502 can easily extract and insert SSM information in T1 and E1 modes, and it supports 2Mb/s signals. In the E1 circuit, the Sa bit is used to send and receive synchronization status information. The most basic Sa/Si bit reading method can be based on CRC4 multi-frame mode or double-frame mode. Through the software interface of DS26502, it can be read and written Sa/Si bits received and sent. In T1 mode, DS26502 directly reads and writes synchronization status information through the BOC controller.
The system initialization and configuration of the single board in Figure 3 are as follows: DS26502 will automatically reset immediately after power-on, clear all the writable register space, and wait for the reset to complete, you can check the device ID number by querying the register. After power-on reset, the LIRST (LIC2.6) register needs to be set from 0 to 1 to reset the line interface circuit. This will initialize the state machine of the clock recovery circuit and re-center the jitter attenuator. This process probably requires 40ms. In addition to the power-on reset, the board can be reset by hardware at any time by pulling down the TSTRST pin, or by software reset by the SFTRST bit in the mode register, and all operations will be interrupted during the reset process. After the reset is complete, the system starts to configure the clock, and after the clock system is allowed to adjust appropriately, it starts to initialize the register space, including writing the reserved bits of the register. Because the system turns off all interrupts by default after reset, you need to write 1 to the specific bit in the interrupt control register to turn on the corresponding interrupt. Therefore, according to the specific application, initialize the interrupt register and turn on different interrupt bits. At this time, the system can work normally and wait. Handling various status information of interrupts and locks. When an interrupt occurs, the system first reads the interrupt information register to determine which status register generated the interrupt, and then checks the status register to finally determine the real interrupt source.
Aiming at the current status of the synchronization network, this article uses the BITS interface chip DS26502 to design a front-end interface circuit, which fulfills the various requirements of ANSI/ITU-T and other standards organizations on network clocks.