As a variety of new packaging types gradually become the mainstream, advanced packaging interconnection technology is facing a turning point in its development. Some suppliers choose to expand the traditional bump packaging method, while others introduce new packaging technology to replace it.
In any case, the goal is to ensure signal integrity between IC package components as the amount of data to be processed increases. But as equipment continues to shrink, and more and more components are added to advanced packaging to process, move, and store more data, new technologies with more I/O will be required. Therefore, although traditional solder balls and/or copper micro bumps will still be used in the foreseeable future, new technologies that enhance or replace traditional interconnection technologies, increase the number of I/Os, and provide more miniature space are being developed. middle.
As always, size and cost are the decisive factors. Copper micro bumps are smaller than solder balls/bumps, allowing more I/O in the package. At present, the micro bump pitch of advanced packaging technology is as small as 40μm, which is equivalent to the bump size of 20μm to 25μm, and the distance between adjacent bumps on the bare die is 15μm.
Figure 1: 2.5D/3D system architecture with HBM3 memory. Copper micro bumps connect the interposer and the substrate. Micro bumps are also used for chip-to-chip connections. Image source: Rambus
For pitches less than 40μm, customers have other options in packaging. First, they can use the existing bumping technology to develop new packaging technologies to break through the technical bottleneck and shrink the current 40μm pitch down to 10μm. Another option is a new technology called copper hybrid bonding. In hybrid bonding technology, the connection of the die is not through the bumps in the package. Instead, the technology uses tiny copper-to-copper interconnects to achieve a narrower pitch package with more I/O than traditional packages. For packaging technology, the pitch of hybrid bonding is at least 10μm and below.
AMD has plans to use hybrid bonding technology in future processor products. The company is using TSMC’s hybrid bonding technology. Other foundries are also studying hybrid bonding. But not all packages require hybrid bonding, and the technology is aimed at high-end products. Even so, hybrid bonding is still an expensive and difficult process.
Intel and other companies have not turned to hybrid bonding, but hope to expand existing bump interconnect technologies and develop packages with pitches less than 40μm around these technologies. “While maintaining compatibility with existing silicon and packaging technologies, it may still be advantageous to use existing infrastructure to shrink solder microbump interconnects to smaller pitches,” Intel’s packaging development engineer Zhaozhi Li said in a recent report. Said at the ECTC conference.
Intel described a method to reduce or reduce the bump pitch to 10μm. Some OSATs are also studying copper bumping technology with a narrower pitch. However, as the solder/copper bump technology gradually shrinks to a narrower pitch, the challenges it faces also increase. There is an increasing demand for new materials, new processes and new tools. Nevertheless, the next generation of bumping technology and hybrid bonding will play an important role in the industry, pushing the technology toward more advanced packaging and Chiplet models. For Chiplet, the chip manufacturer may have a modular die menu in the library. Then, customers can mix and match chips and integrate them into existing package types or new architectures.
Chiplet is becoming an alternative to advancing chip design. Traditionally, in order to advance the design, vendors will develop system-on-chip (SoC) and integrate more functions on each generation of devices. But with the delay of Moore’s Law, chip integration becomes more and more difficult and expensive. Although this method is still an option for new designs, Chiplet is expected to become the next generation chip design trend. Hybrid bonding or scaling bumps are a key part of the Chiplet puzzle.
Packaging technology overview
IC packaging wraps the die in a closed cell to protect the device from damage. Packaging can also improve the performance of the die.
“The industry is increasing investment in advanced packaging, and is committed to increasing system-level interconnect density, reducing power consumption, achieving smaller form factors, and reducing package-level spacing and integrating more functions into a single package. Reduce costs.” said Xiao Liu, senior project manager at Brewer Science. The industry has developed more than 1,000 different packaging technologies. Customers can choose according to a given application.
The packaging market is segmented according to interconnection types, including wire bonding, flip chip, wafer level packaging (WLP) and through silicon via (TSV). TSV provides the most I/O, followed by WLP, flip chip and wire bonding.
According to TechSearch, approximately 75% to 80% of packages are based on wire bonding. Wire bonders use thin wires to stitch one chip onto another chip or substrate. Wire bonders are used to manufacture commodity and mid-range packages and memory stacks.
Flip chips form tiny solder or copper bumps on top of the chip. The device is then turned over and mounted on a separate die or board. The bumps land on the copper pads, forming electrical connections.
In this process, a high-speed flip chip bonding machine is used to connect the bump die, and then a large-scale reflow process is performed. “Many flip-chip devices do not require narrow pitch. They can be completed by large-scale reflow,” said Bob Chylak, CTO of Kulicke & Soffa (K&S). “The flip chip bonder takes out the chips, dips the solder balls into the flux, and places them on the PCB. Then the PCB passes through a reflow oven, which melts the solder and then solidifies it.”
Flip chip is used to develop many package types, such as ball grid array (BGA). The graphics chip and processor are packaged in BGA. In flip chip, the bump pitch on the chip ranges from 300μm to 50μm.
“We still see wide-pitch packages ranging from 140μm to 150μm. This technology is still the mainstream of development and will not change soon,” said Annette Teng, Promex CTO, QP Technologies’ parent company. “We are beginning to see some packaging technologies ranging from 110μm to 120μm. Below 40μm is still in the development stage.”
At the same time, fan-out packaging is a wafer-level packaging. In an example of fan-out packaging, DRAM die are stacked on a logic chip.
TSV is used in advanced 2.5D/3D packages and is usually used in high-end systems. In the 2.5D/3D package, the dies are stacked or placed side by side on top of the interposer, and the interposer contains TSV. TSV provides the electrical connection from the die to the circuit board. In an example of 2.5D, ASIC and high bandwidth memory (HBM) are placed side by side on the interposer. (HBM is the DRAM memory stack.)
2. The solder balls of the 5D package are located at the bottom of the substrate to electrically connect the package with the circuit board. C4 bumps are smaller structures that connect the substrate to the interposer. Small copper micro bumps connect the interposer to the substrate. In HBM, the DRAM die is connected by tiny micro bumps with a pitch of 40μm.
In order to stack and connect the die in these packages, a thermal compression bonder (TCB) system picks up the die and aligns the bumps with the bumps of another die. The system uses pressure and heat to bond the bumps.
Looking to the future, suppliers hope to develop HBM modules and 3D packages with bump pitches less than 40μm to achieve more I/O and bandwidth. Chip customers can develop advanced packages by using finer bumps or using copper hybrid bonding. Some customers may use these two methods at the same time for different packages.
The pitch of copper bumps is expected to shrink from 40μm to 10μm. Then, the packaging technology gradually moved towards hybrid bonding, so as to realize the interconnection with pitch of 10μm and below. But not all packaging plants can develop hybrid bonding. For most OSATs, this technology is too costly and requires expensive semiconductor fabs to implement these processes.
Selected foundries are the only method for suppliers to put hybrid bonding into production. Even so, hybrid bonding for packaging is still challenging. “The huge challenges facing hybrid bonding are wafer surface cleanliness, wafer warpage, and the gradient between copper and dielectric materials in the chip,” said Tony Lin, UMC technical director.
Hybrid bonding still faces many problems. “The next few years will definitely introduce products with very narrow pitch (using hybrid bonding).” said Mike Kelly, vice president of advanced packaging development and integration at Amkor. “This is an expensive process and may still be the leader in ultra-high performance in the next few years.”
With this in mind, Intel and other companies are using traditional micro bumps below 40μm to develop new advanced packaging technologies. Suppliers are also studying the next-generation HBM technology HBM3, which has twice the bump density of HBM2e. HBM3 supports a bandwidth of 8.4Gbps, while the bandwidth of HBM2e is 3.6Gbps.
Miniature bumps have the following advantages. First, it utilizes the existing solder/copper bump infrastructure. Secondly, several suppliers are studying narrow pitch bump technology, such as Amkor, ASE, Intel, JCET, Samsung and TSMC.
The development of packaging technology with bumps is not new. In 1960, flip chip packaging emerged as an assembly technology. Initially, the flip-chip process involved the formation of C4 (Controlled Collapse Chip Connection) bumps with diameters ranging from 75μm to 200μm.
C4 bumps are still used in packages, but they are a wide pitch structure. Therefore, starting from the 65nm node in 2006, Intel and other companies have gradually migrated to a smaller version of C4 bumps, called copper micro bumps/pillars, sometimes also called C2 bumps. The original copper microbumps have a diameter of 25μm.
The copper bumps consist of copper pillars with a thin nickel diffusion barrier and tin-silver solder caps. “C2 bumps provide better thermal and electrical performance than C4 bumps. This is because the thermal conductivity and resistivity of Cu are better than solder,” Unimicron CTO John Lau wrote in his new book “Semiconductor Advanced Packaging” (Springer, 2021).
In order to make smaller copper micro bumps, the process is similar to the C4 process. First, the chips are processed on wafers in the fab. Then, bumps are formed on the bottom of the wafer.
To this end, a deposition method is used to deposit the surface through an under-bump metallization (UBM) layer. Then, apply a photosensitive material called photoresist on UBM. A photolithography system is used to pattern a predetermined bump size on top of the resist. The pattern is etched to form a small gap.
Use an electrochemical deposition (ECD) system to fill the gap or plate the gap with copper. Strip the resist and etch the structure. The structure is refluxed or heated in an oven to form bumps.
Figure 2: Process flow of micro bumps. Source: John Lau, Unimicron
Today’s most advanced micro bumps use 40μm pitch and bump sizes between 20μm and 25μm. According to DuPont, the bump size is about 50% of the bump pitch.
Future packaging will shift to smaller copper bumps with narrower pitches. “We see that the pillar bump size has 18μm pitch, 9μm diameter and 20μm height. There are about 200 million bumps on a 300mm wafer with a pitch of 18 microns.” Onto Innovation product marketing manager Woo Young Han said. “We heard that a customer claimed to achieve 10μm pitch, 5μm diameter and 10μm height. There are about 500 million bumps on a 300mm wafer with 10μm pitch. The 5μm bump diameter is the smallest diameter we heard from customers .”
Researching into smaller bumps presents some challenges. “As the solder bump pitch shrinks, the bump height becomes shorter, the bump surface that can be used for bonding decreases, and the number of chip-level bumps increases,” Han said. “As the number of bumps increases, the reduction in bump size translates into a smaller error margin to establish a reliable electrical connection. As the bump pitch shrinks, chip-level bump coplanarity and bump surface roughness Degree and bump hardness are becoming more and more important. The temperature, time and pressure used in the bonding process depend on the quality of chip-level bump coplanarity, bump surface roughness and bump hardness. During the bonding process The use of higher temperatures, longer times and greater pressure will increase the cost and risk of damaging the chip.”
All of these present several challenges throughout the manufacturing process. Take etching as an example. “The diameters of copper pillars and solder bumps are smaller. Undercuts due to etching are becoming more and more important,” said Lau of Unimicron.
The ECD plating process also faces challenges. “As customers target next-generation micro-bump solutions, plating uniformity and coplanarity control becomes more and more important,” said Manish Ranjan, managing director of Lam Research. “Lam’s electroplating bath design can provide ultra-high uniform convection to achieve a fast and uniform deposition rate. In addition, proprietary technical solutions, such as advanced surface treatment capabilities, can achieve the lowest defect performance.”
Most importantly, the transition to smaller bumps may also require new and differentiated bump structures. Consider a micro bump with a pitch of 40 μm and a bump height of 25 μm. In this bump, the height of the copper structure is 15μm, and the height of the nickel is 5μm. The remaining part is the welding cap.
“In this structure, copper is larger than nickel,” said Shashi Gupta, head of global marketing for DuPont’s advanced packaging technology. “When you use a narrower pitch, the height of the copper will start to shrink. At some point, the thickness of the copper is more or less the same as the thickness of the nickel. The welding cap is also shrinking.”
In a hypothetical example, the future copper pillar may have a 3μm copper structure, a 3μm nickel barrier layer and a 5μm solder cap. “The key is that nickel and copper are very similar. At this thickness, it is a challenge to maintain uniformity across the wafer,” Gupta said. “Therefore, you may want to consider choosing a metal in the columnar structure with the solder on top.”
In other words, in a narrower pitch package, you may have a tiny copper pillar with a solder cap, or a nickel pillar with a solder cap. “For cost, yield or performance considerations, copper/tin-silver or nickel/tin-silver structures are usually used instead of copper/nickel/tin-silver structures,” Gupta said. “This will help optimize the cost structure and make it easier to control quality.”
Compared with nickel, copper is a better metal, but copper also has some disadvantages. Nickel has lower conductivity, but nickel bumps may also play a role. This is still in the research and development stage, and it is not clear how nickel is used in production.
Nevertheless, in future processes, copper bumps will only require copper plating, while nickel bumps will use nickel plating.
This in turn simplifies the electroplating process. “It is easier to plate a single layer of copper or nickel than plating two layers (plating copper first, then nickel). Then put the same solder on it in a reduced volume,” Gupta said.
In the end, the two different bump metals are combined and diffused into each other’s grain boundaries. This is called an intermetallic compound (IMC) layer. In some cases, IMC is solid. In other cases, the IMC is fragile, causing the connection to fail.
IMC is where problems may arise. “For copper/tin-silver bump structures, where the solder is deposited directly on the copper pillars without a nickel barrier layer, an intermetallic compound (IMC) layer may be formed during reflow,” Gupta said. “The IMC layer may continue to grow during the aging or heating process, which has a negative impact on the reliability and conductivity of the solder joint. In contrast, a uniform nickel plating instead of a copper pillar can effectively limit a wide range of IMC growth and provide excellent Barrier capabilities, solderability, and other characteristics are essential for consistent wafer manufacturing. From a process point of view, newer nickel-based plating options are also sustainable.”
Figure 3: Universal pillar design and advanced micro pillar design. Source: DuPont
Making tiny bumps is extremely challenging. It is also difficult to bond them together at a narrower pitch.
Traditional flip-chip bonding through large-scale reflow faces challenges in narrower pitches. “The standard reflow process is performed in an oven for flip-chip and system-in-package. The solution is known for its quantity and low price,” said Nokibul Islam, senior director of field application engineering at JCET. “The concern is that there may be a mismatch in the overall thermal expansion coefficient between the substrate and the chip, which can lead to higher warpage and chip displacement.”
The traditional flip chip process can be applied to 50μm or 40μm pitch, but further down, reliability problems may occur. This is where TCB applies. As early as a few years ago, TCB has been launched for advanced narrow pitch bonding applications. Some vendors are selling TCB tools.
TCB tools are used to bond bare dies with tiny bumps with a pitch of 40μm to 50μm and below, and are suitable for chip-to-wafer and chip-to-substrate applications. As far as the current situation is concerned, TCB is scaled down to 10μm pitch.
“The thermocompression bonding is partial reflow,” said Chylak of K&S. “Instead of heating the entire circuit board and all the chips on it, the thermocompression soldering machine grabs the chip like a normal flip chip, dips it in the flux, and then places it on the PCB. There are A heater. It heats to above the melting point of the solder holding the chip in place. Then it cools down to solidify the solder.”
Flux is used to remove oxides on the copper pads that are trying to bond. In the chemical reaction, the flux will dissolve the oxide.
However, TCB is a relatively slow process, and there are some flux cleaning issues. “Flip-chip and thermocompression bonding have problems. The flux immersed in the bumps must be clean.” Chylak said.
The industry uses cleaning systems to remove the flux in the package. This is suitable for wide-pitch applications, but this process requires time to clean the flux for narrow-pitch packages.
In another possible solution, the industry has developed a “no-clean flux” material. These materials are not always effective. If flux appears in the process, it will be difficult to clean.
Therefore, K&S is developing flux-free TCB technology. In the TCB tool, K&S combines an in-situ formic acid vapor delivery system and chamber. “We can put a layer of formic acid vapor, which can clean the surface without flux, and then we perform bonding. This is a new technology we developed that can bond without flux. This is for TCB Improvements in productivity and reliability,” Chylak said.
There are other solutions. On ECTC, as part of ASE, Siliconware described a method for developing a 3D package with a 20μm bump pitch, aimed at stacking and bonding two thin chips. There are two test scenarios. One uses TCB with capillary underfill (TCCUF). The other uses TCB with non-conductive paste (TCNCP).
“All in all, we have successfully characterized and developed a 3D packaging technology using a 20?m bump pitch. This packaging technology can be achieved through standard die mounting and reflow, as well as thermocompression soldering using NCF,” Siliconware Said Mu Hsuan Chan, technical manager of.
At the same time, Intel found a way to shrink micro bumps with 20μm and 10μm pitches. Intel has developed bare dies with tiny bumps and bonded them together with a TCB tool with an alignment accuracy better than 2.1μm.
“The data shows that it is feasible to use powerful TCB tools and tight bonding process control to configure Cu/SnAg micro bumps at a pitch of 20μm. However, at 10μm, in order to retain solder to meet the needs of TCB bonding , And to obtain sufficient bonding process margin, a certain amount of solder/Cu diffusion barrier metal needs to be placed.” Intel’s Li said.
Eventually, Intel and other companies will adopt hybrid bonding technology. TSMC hopes to make breakthrough progress in this technology as soon as possible.
But whether it is narrow-pitch packaging or wide-pitch packaging, bump packaging technology will continue to develop in the future. Nevertheless, both advanced bumping and hybrid bonding will provide narrow-pitch interconnects for new advanced packaging technologies. More than one packaging technology option is very good for companies.