A simple ratio technique for measuring extremely low resistance

A common application for Z of very low value resistors (ie, milliohms (mΩ) and below) may be current control circuits, and their low value can reduce power loss. For these applications, a tolerance of approximately 10%-20% is sufficient. But even under these tolerances, it is quite difficult for JQ to measure very low resistance values, especially when large currents are involved.

A common application for Z of very low value resistors (ie, milliohms (mΩ) and below) may be current control circuits, and their low value can reduce power loss. For these applications, a tolerance of approximately 10%-20% is sufficient. But even under these tolerances, it is quite difficult for JQ to measure very low resistance values, especially when large currents are involved.

The circuit shown in Figure 1 provides a solution to this problem by applying low duty cycle pulses to an unknown resistor and a reference resistor of known value. The ratio technique is used to compare the responses of two components and determine the value of the resistance being measured.

A simple ratio technique for measuring extremely low resistance

The circuit shown in Figure 1 applies low duty cycle pulses to an unknown resistor and a reference resistor of known value, allowing JQ to measure extremely low resistance values.

The measured value needed to calculate the JQ resistance value can be obtained from the output V1 and V2 using a common oscilloscope or pulse peak voltmeter, which can provide a higher JD.

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This circuit uses the old 555 timer, which runs in an astable mode to generate pulses for charging and discharging the low inductance capacitor C2. During the discharge cycle, current flows through the precision standard resistor (R6) and the measured resistance (Rx). The resistance value can be calculated by the ratio of the corresponding voltage:

V1 / V2 = (Rx R6) / R6 = Rx / R6 1,

Among them, V1 and V2 are peak values.

Therefore, the unknown value:

Rx = (V1 / V2 C 1) * R6

The bandwidth of the oscilloscope/voltmeter should be large enough to capture the short pulses generated by the circuit. Because the ratio of the half period of the 555 oscillator to the pulse duration is very large, some oscilloscopes cannot ensure sufficient brightness.

This circuit can also be used to drive other low-resistance loads that require high-amplitude, low-duration current pulses, such as semiconductor lasers.

Test circuit details

Pulse synchronization (U1, pin 3) is conducive to the early synchronization of the oscilloscope; the delay between the synchronization and the output pulse may cause the oscilloscope to capture the leading edge of the pulse, because some oscilloscopes may not have a delay line in the Y channel, which makes it impossible to Display Very steep frontier. The delay is determined by the time constant R3 * C3. The value of C3 may be in the range of 20 C 500pF (or even more), depending on the time base used and the oscilloscope itself.

The MOSFET driver U2 (TC4422A) is used to ensure high gate charging current and fast on-time of Q1, which is essential for JQ measurement.

The MOSFET (Q1) has a very low R DSOn (less than 3Ω) to ensure clean high-amplitude pulses. The fast diode D2 limits the overvoltage of Q1. Note: The high current in this part of the circuit requires special attention to component selection and PCB layout. For details, please refer to the component selection instructions and design instructions section below.

The short and powerful current pulses of this circuit also produce a broad-spectrum response in the frequency domain. Therefore, special attention must be paid to minimize the parasitic inductance and capacitive load, otherwise the circuit will show a high level of reactance and cause oscillations in various parts of the layout. The practical details you need to know about how to reduce these unwanted parasitic effects to low Z are recorded in the design description section of this article.

Precautions for component selection

SMD components used in circuits are strongly recommended. Some capacitors, even with thin-film-based structures, have their dielectric layer undergoing piezoelectric motion when subjected to sharp high-current pulses, similar to those exposed to C2. Sometimes you can even hear a fairly audible “tick” from this type of capacitor, which means a high level of loss due to the piezoelectric effect. In this case, components with a lower “tick” level can be regarded as better components.

A 0.005 Ω (5 mΩ), 1% tolerance LOB-3 precision resistor from TT Electronics was used as the standard resistor (R6).

Because the circuit uses proportional measurement technology, the tolerance of most components is not critical, but special attention should be paid to their stability and structural style. For example, the value of capacitor C2 is not important, but it should be large enough to provide a long enough current pulse that your oscilloscope or voltmeter can easily notice.

The capacitor should use a construction technology with low internal resistance/inductance, such as laminated foil film or ceramic. You should avoid using many types of capacitors, especially ceramic capacitors, if their capacitance depends on the applied voltage. If necessary, multiple capacitors can be connected in parallel to produce the desired value.

For MOSFETs, good examples with very low R DSon are CSD16321Q5 from TI or IRLx8743 from IR. However, such devices usually have relatively low drain-source and gate-source breakdown voltages (CSD16321Q5 is only 8 V)-this is a potential weakness that you should consider when making any modifications.

Another potential limitation is the large drain current of the MOSFET. Both of these parameters will affect the measurement lower limit of the test circuit.

In order to reduce the level of parasitic oscillations, resistor R6 and capacitor C4 should have very low inductance-the components themselves and the PCB traces to which they are connected.

Design notes

The PCB traces around R6 and C4 must be kept short and laid out to minimize the parasitic reactance with Z. The parasitic reactance will cause the local resonance excited by the current pulse. If the circuit layout does not meet this requirement, it will easily exceed the JDZ large rated voltage of MOSFET Q1. For example, for a capacitive load of 6nF (gate capacitance), the output rise/fall time of the driver TC4422A can be less than 25 ns; this fact, coupled with the large current (~100 A) through the inductor, will cause damage to almost any MOSFET Voltage.

Please refer to the schematic to see the traces highlighted in bold-these traces must be wide enough to carry high currents and as short as possible to minimize parasitic inductance. This is especially important for the trace that connects the gate to the driver (U2, pin 6 to the base of Q1), which should be kept less than 1 inch. The ferrite beads on this trace (B) help to suppress unwanted oscillations.

For the same reason, the connection of resistors Rx and R6 should be as close to the same length as possible. They should also be as short as possible to minimize inductance and voltage drop with Z.

All external connections to the circuit should be designed using basic high-frequency practices. For example, a 50 Ω coaxial cable with good impedance matching at both ends must be used.

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