A/D converter external support circuit design scheme

This application note describes techniques for measuring and maximizing the performance of 120 dB, 24-bit, and 96 kHz analog-to-digital converter integrated circuits. It introduces ADC architecture, input buffer design and its noise requirements, noise calculation and noise analysis. It also describes the external support circuit design and some example results.

This application note describes techniques for measuring and maximizing the performance of 120 dB, 24-bit, and 96 kHz analog-to-digital converter integrated circuits. It introduces ADC architecture, input buffer design and its noise requirements, noise calculation and noise analysis. It also describes the external support circuit design and some example results.

A/D converter architecture

The A/D converter used in this discussion consists of an analog delta sigma modulator chip and a digital filter chip, packaged in a single 28-pin SOIC plastic package. Figure 1 shows the block diagram of the device. Highlights of delta-sigma modulator design include the use of a three-level modulator, which produces excellent linearity after calibration, a novel coding scheme for modulator output data, which eliminates data-related changes in the number and polarity of data signal edges, and Differential design produces low distortion and good common mode rejection. The decimation filter includes multiple word length output options, and optional psychoacoustic noise shaping. Also includes low group delay for real-time use.

A/D converter external support circuit design scheme
A/D converter block diagram

Input buffer design

The input buffer circuit of the A/D converter must meet several strict requirements. These include: negligible noise contribution, DC level shift from an input signal usually centered at zero volts to an output signal centered on the common-mode voltage of the A/D converter, and isolation of buffer amplifiers from switched capacitor current transients , While keeping the output impedance low, so as not to cause distortion, and provide anti-aliasing filtering suitable for the modulator sampling rate.

A/D converter external support circuit design scheme
Input buffer circuit diagram

Figure 2 shows the servo balanced differential input buffer circuit chosen for this application. The circuit provides the required differential output through a differential or single-ended signal of either polarity on the input terminal. The gain structure of the input buffer is designed to attenuate the 25.5 dBu (1.414 Vrms) required to produce a 0 dBFS digital output.The 6 dB attenuation in the buffer input structure is followed by a resistor network at the input of the A/S converter, which provides an additional 13.3 dB attenuation

External support circuit design

The performance of the A/D converter may be degraded due to improper design of the external environment. This section introduces the direct environment around the A/D converter, including ground plane recommendations, decoupling capacitor selection, correct clock generator connection, and overvoltage protection.

Test setup instructions

A/D converter external support circuit design scheme
Test setup signal flow

Figure 3 shows the main components of the test setup. The goal of this setup is to provide as favorable an environment as possible so that the A/D converter can exert its best performance. The Audio Precision System 2 was used as an analog test signal generator, and some measurement results were confirmed at a sampling rate of 48 kHz. The PC is used to control the A/D converter through its control port, and is also used to collect 96 kHz A/D converter output data. Custom software running on the PC allows control of the A/D converter and FET analysis of the output data.

The Links:   NL6448AC33-24 LQ9D021

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